Architecture of Computing Systems: Lecture Notes in Computer Science, cartea 12800
Editat de Christian Hochberger, Lars Bauer, Thilo Piontecken Limba Engleză Paperback – 15 iul 2021
The 12 full papers in this volume were carefully reviewed and selected from 24 submissions. 2 workshop papers (VEFRE) are also included. ARCS has always been a conference attracting leading-edge research outcomes in Computer Architecture and Operating Systems, including a wide spectrum of topics ranging from fully integrated, self-powered embedded systems up to high-performance computing systems. It also provides a platform covering newly emerging and cross-cutting topics, such as autonomous and ubiquitous systems, reconfigurable computing and acceleration, neural networks and artificial intelligence. The selected papers cover a variety of topics from the ARCS core domains, including heterogeneous computing, memory optimizations, and organic computing.
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Specificații
ISBN-13: 9783030816810
ISBN-10: 3030816818
Pagini: 248
Ilustrații: XVIII, 229 p. 81 illus., 67 illus. in color.
Dimensiuni: 155 x 235 x 14 mm
Greutate: 0.38 kg
Ediția:1st edition 2021
Editura: Springer
Colecția Lecture Notes in Computer Science
Seria Lecture Notes in Computer Science
Locul publicării:Cham, Switzerland
ISBN-10: 3030816818
Pagini: 248
Ilustrații: XVIII, 229 p. 81 illus., 67 illus. in color.
Dimensiuni: 155 x 235 x 14 mm
Greutate: 0.38 kg
Ediția:1st edition 2021
Editura: Springer
Colecția Lecture Notes in Computer Science
Seria Lecture Notes in Computer Science
Locul publicării:Cham, Switzerland
Cuprins
Memory Organization.- Locality: The 3rd Wall and The Need for Innovation in Parallel Architectures.- Static extraction of memory access profiles for multi-core interference analysis of real-time tasks.- Transparent Resilience for Approximate DRAM.- Heterogeneous Computing.- Automatic Mapping of Parallel Pattern-based Algorithms on Heterogeneous Architectures.- Assessing and Improving the Suitability of Model-Based Design for GPU-Accelerated Railway Control Systems.- DRT: A Lightweight Runtime for Developing Benchmarks for a Dataflow Execution Model.- Instruction Set Transformations.- Performance Gain of a Data Flow Oriented ISA as Replacement for Java Bytecode.- Towards Transparent Dynamic Binary Translation from RISC-V to a CGRA.- Organic Computing.- An Organic Computing System for Automated Testing.- Evaluating a Priority-Based Task Distribution Strategy for an Artificial Hormone System.- Low Power Design.- Streamlining the OpenMP Programming Model on Ultra-Low-Power Multi-Core MCUs.- Energy Efficient Power-Management for Out-of-Order Processors using Cyclic Power-Gating.- VEFRE Workshop.- BCH 2-Bit and 3-Bit Error Correction with Fast Multi-Bit Error Detection.- Evaluating Soft Error Mitigation Trade-offs During Early Design Stages.