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Analog Circuit Design: RF Analog-to-Digital Converters; Sensor and Actuator Interfaces; Low-Noise Oscillators, PLLs and Synthesizers de Rudy J. van de Plassche

Analog Circuit Design: RF Analog-to-Digital Converters; Sensor and Actuator Interfaces; Low-Noise Oscillators, PLLs and Synthesizers

Editat de Rudy J. van de Plassche, Johan Huijsing, Willy M.C. Sansen
en Limba Engleză Paperback – 7 dec 2010
This new book on Analog Circuit Design contains the revised contributions of all the tutorial speakers of the eight workshop AACD (Advances in Analog Circuit Design), which was held at Nice, France on March 23-25, 1999. The workshop was organized by Yves Leduc of TI Nice, France. The program committee consisted of Willy Sansen, K.U.Leuven, Belgium, Han Huijsing, T.U.Delft, The Netherlands and Rudy van de Plassche, T.U.Eindhoven, The Netherlands. The aim of these AACD workshops is to bring together a restricted group of about 100 people who are personally advancing the frontiers of analog circuit design to brainstorm on new possibilities and future developments in a restricted number of fields. They are concentrated around three topics. In each topic six speakers give a tutorial presentation. Eighteen papers are thus included in this book. The topics of 1999 are: (X)DSL and other communication systems RF MOST models Integrated filters and oscillators The other topics, which have been coverd before, are: 1992 Operational amplifiers A-D Converters Analog CAD 1993 Mixed-mode A+D design Sensor interfaces Communication circuits 1994 Low-power low-voltage design Integrated filters Smart power 1995 Low-noise low-power low-voltge design Mixed-mode design with CAD tools Voltage, current and time references vii viii 1996 RF CMOS circuit design Bandpass sigma-delta and other data converters Translinear circuits 1997 RF A-D Converters Sensor and actuator interfaces Low-noise oscillators, PLL's and synthesizers 1998 I-Volt electronics Design and implementation of mixed-mode systems Low-noise amplifiers and RF power amplifiers for telecommunications
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Specificații

ISBN-13: 9781441951854
ISBN-10: 1441951857
Pagini: 432
Ilustrații: VIII, 420 p.
Dimensiuni: 155 x 235 x 23 mm
Greutate: 0.6 kg
Ediția:Softcover reprint of hardcover 1st ed. 1997
Editura: Springer Us
Colecția Springer
Locul publicării:New York, NY, United States

Public țintă

Research

Cuprins

I: RF Analog-to-Digital Converters.- Design of a Silicon Bipolar Track&Hold IC for 1gsample/s and 10 bit Linearity over the full Nyquist Band.- Power and Scaling Rules of CMOS High-Speed A/D Converters.- An Embedded 170-mW 10-BIT 50-MS/s CMOS ADC IN 1-mm2.- Architectures and Circuits for A/D and D/A Conversion in CMOS Integrated Systems for Telecom Applications.- A 12 bit, 50 Msample/s Cascaded Folding & Interpolating ADC.- Linearizing a 128 Msample/s ADC.- II: Sensor and Actuator Interfaces.- Advances in State-of-the-Art in Smart Sensor Signal Conditioning.- Low-Power Sensor Interfaces.- Capacitive Interfaces for Monolithic Integrated Sensors.- Low-Cost Interfaces for Sensors and Sensor Systems.- Integrated Sensor Systems in CMOS Technology.- Compensation and Calibration of IC Microsensors.- III — Low-noise oscillators, PLL’s and Synthesizers.- How Phase Noise Appears in Oscillators.- Synthesizer Architectures.- Fully Integrated Low Phase-Noise VCOs: from Post-Processing to Standard CMOS.- Modeling and Simulation of Jitter in Phase-Locked Loops.- Phase Noise, Signal Power and Current Consumption in CMOS Colpitts Oscillators.- Noise in Fully Integrated PLL’s.

Recenzii

`The authors are to be complimented for collecting, into a single reference, a lot of interesting information related to the above mentioned topics, particularly useful for data-acquisition system designers, RF engineers, and others.'
Microelectronics Journal 29 (1998) 1039-1046

Descriere

Descriere de la o altă ediție sau format:
The realization of signal sampling and quantization at high sample rates with low power dissipation is an important goal in many applications, includ­ ing portable video devices such as camcorders, personal communication devices such as wireless LAN transceivers, in the read channels of magnetic storage devices using digital data detection, and many others. This paper describes architecture and circuit approaches for the design of high-speed, low-power pipeline analog-to-digital converters in CMOS. Here the term high speed is taken to imply sampling rates above 1 Mhz. In the first section the dif­ ferent conversion techniques applicable in this range of sample rates is dis­ cussed. Following that the particular problems associated with power minimization in video-rate pipeline ADCs is discussed. These include optimi­ zation of capacitor sizes, design of low-voltage transmission gates, and opti­ mization of switched capacitor gain blocks and operational amplifiers for minimum power dissipation. As an example of the application of these tech­ niques, the design of a power-optimized lO-bit pipeline AID converter (ADC) that achieves =1. 67 mW per MS/s of sampling rate from 1 MS/s to 20 MS/s is described. 2. Techniques for CMOS Video-Rate AID Conversion Analog-to-digital conversion techniques can be categorized in many ways. One convenient means of comparing techniques is to examine the number of "analog clock cycles" required to produce one effective output sample of the signal being quantized.