Analog Circuit Design: Mixed A/D Circuit Design, Sensor Interface Circuits and Communication Circuits
Editat de Willy M.C. Sansen, Johan Huijsing, Rudy J. van de Plasscheen Limba Engleză Paperback – 7 dec 2010
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Specificații
ISBN-13: 9781441951380
ISBN-10: 1441951385
Pagini: 332
Ilustrații: VIII, 318 p.
Dimensiuni: 155 x 235 x 17 mm
Greutate: 0.52 kg
Ediția:Softcover reprint of the original 1st ed. 1994
Editura: Springer Us
Colecția Springer
Locul publicării:New York, NY, United States
ISBN-10: 1441951385
Pagini: 332
Ilustrații: VIII, 318 p.
Dimensiuni: 155 x 235 x 17 mm
Greutate: 0.52 kg
Ediția:Softcover reprint of the original 1st ed. 1994
Editura: Springer Us
Colecția Springer
Locul publicării:New York, NY, United States
Public țintă
ResearchCuprins
I: Mixed Analogue-Digital Circuit Design.- Groundbounce in CMOS.- Design Aspects for Mixed Analog-Digital Circuits.- Design Aspects Using ELDO.- Simulation of a Floppy Disk Drive Head Position Controller.- Mixed Signal ASIC Design.- Mixed Signal ASIC Design for Automotive and Industrial Applications.- II Sensor Interface Circuits.- Sensor Signal Normalization.- Analog Data Acquisition Circuits in Integrated Sensing Systems.- Integrated Interface Circuits for Capacitive Micromechanical Sensors.- Interfaces for Microsensor Systems.- Sensor Interface Systems.- Indirect Converters and Oversampling for Application in Monolithic Smart Sensors.- III: Communication Circuits.- The Challenges for Analog Circuit Design in Mobile Radio VLSI Chips.- A View of Gallium Arsenide I.C.’s in Wireless Communication Systems.- Design Techniques for 1GHz Downconversion ICs Fabricated in a 1?m 13GHz BiCMOS Process.- New RF Devices Based on High Precision CMOS Time-to-Digital and Digital-to-Time Converters.- A Fully Integrated 1 V/ 100?A high Bitrate CP-FSK receiver.- DECT Zero IF Receiver Front End.
Recenzii
`The authors are to be complimented for collecting, into a single reference, a lot of interesting information related to the above mentioned topics, particularly useful for data-acquisition system designers, RF engineers, and others.'
Microelectronics Journal 29 (1998) 1039-1046
Microelectronics Journal 29 (1998) 1039-1046
Descriere
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The realization of signal sampling and quantization at high sample rates with low power dissipation is an important goal in many applications, includ ing portable video devices such as camcorders, personal communication devices such as wireless LAN transceivers, in the read channels of magnetic storage devices using digital data detection, and many others. This paper describes architecture and circuit approaches for the design of high-speed, low-power pipeline analog-to-digital converters in CMOS. Here the term high speed is taken to imply sampling rates above 1 Mhz. In the first section the dif ferent conversion techniques applicable in this range of sample rates is dis cussed. Following that the particular problems associated with power minimization in video-rate pipeline ADCs is discussed. These include optimi zation of capacitor sizes, design of low-voltage transmission gates, and opti mization of switched capacitor gain blocks and operational amplifiers for minimum power dissipation. As an example of the application of these tech niques, the design of a power-optimized lO-bit pipeline AID converter (ADC) that achieves =1. 67 mW per MS/s of sampling rate from 1 MS/s to 20 MS/s is described. 2. Techniques for CMOS Video-Rate AID Conversion Analog-to-digital conversion techniques can be categorized in many ways. One convenient means of comparing techniques is to examine the number of "analog clock cycles" required to produce one effective output sample of the signal being quantized.
The realization of signal sampling and quantization at high sample rates with low power dissipation is an important goal in many applications, includ ing portable video devices such as camcorders, personal communication devices such as wireless LAN transceivers, in the read channels of magnetic storage devices using digital data detection, and many others. This paper describes architecture and circuit approaches for the design of high-speed, low-power pipeline analog-to-digital converters in CMOS. Here the term high speed is taken to imply sampling rates above 1 Mhz. In the first section the dif ferent conversion techniques applicable in this range of sample rates is dis cussed. Following that the particular problems associated with power minimization in video-rate pipeline ADCs is discussed. These include optimi zation of capacitor sizes, design of low-voltage transmission gates, and opti mization of switched capacitor gain blocks and operational amplifiers for minimum power dissipation. As an example of the application of these tech niques, the design of a power-optimized lO-bit pipeline AID converter (ADC) that achieves =1. 67 mW per MS/s of sampling rate from 1 MS/s to 20 MS/s is described. 2. Techniques for CMOS Video-Rate AID Conversion Analog-to-digital conversion techniques can be categorized in many ways. One convenient means of comparing techniques is to examine the number of "analog clock cycles" required to produce one effective output sample of the signal being quantized.