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Analog Circuit Design: High-Speed Analog-to-Digital Converters, Mixed Signal Design; PLLs and Synthesizers de Rudy J. van de Plassche

Analog Circuit Design: High-Speed Analog-to-Digital Converters, Mixed Signal Design; PLLs and Synthesizers

Editat de Rudy J. van de Plassche, Johan Huijsing, Willy M.C. Sansen
en Limba Engleză Paperback – 2 dec 2010
This book contains the extended and revised editions of all the talks of the ninth AACD Workshop held in Hotel Bachmair, April 11 - 13 2000 in Rottach-Egem, Germany. The local organization was managed by Rudolf Koch of Infineon Technologies AG, Munich, Germany. The program consisted of six tutorials per day during three days. Experts in the field presented these tutorials and state of the art information is communicated. The audience at the end of the workshop selects program topics for the following workshop. The program committee, consisting of Johan Huijsing of Delft University of Technology, Willy Sansen of Katholieke Universiteit Leuven and Rudy van de Plassche of Broadcom Netherlands BV Bunnik elaborates the selected topics into a three-day program and selects experts in the field for presentation. Each AACD Workshop has given rise to publication of a book by Kluwer entitled "Analog Circuit Design". A series of nine books in a row provides valuable information and good overviewsof all analog circuit techniques concerning design, CAD, simulation and device modeling. These books can be seen as a reference to those people involved in analog and mixed signal design. The aim of the workshop is to brainstorm on new and valuable design ideas in the area of analog circuit design. It is the hope of the program committee that this ninth book continues the tradition of emerging contributions to the design of analog and mixed signal systems in Europe and the rest of the world.
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Specificații

ISBN-13: 9781441950024
ISBN-10: 1441950028
Pagini: 420
Ilustrații: VIII, 408 p.
Dimensiuni: 160 x 240 x 22 mm
Greutate: 0.59 kg
Ediția:Softcover reprint of hardcover 1st ed. 2000
Editura: Springer Us
Colecția Springer
Locul publicării:New York, NY, United States

Public țintă

Research

Cuprins

I: High-Speed Analog-to-Digital Converters.- Speed-Power-Accuracy Trade-off in high-speed Analog-to-digital converters: Now in the future....- A dual mode 700 Msamples/s 6-bit, 200 Msamples/s 7-bit A/D converter in 0.25 micron digital CMOS.- A 3.3 V 12b 50-Ms/s A/D converter in 0.6 micron CMOS with over 80-dB SFDR.- A 10-bit 20–30 MSPS CMOS subranging ADC with 9.5 Effective bits at Nyquist.- A 2.5 MHz output-rate delta-sigma ADC with 90dB SNR and 102dB SFDR.- A 13-bit bandpass sigma-delta modulator for 10.7 MHz digital IF with a 40 MHz sampling rate.- II: Mixed Signal Design.- System-level design issues for mixed-signal ICs and telecom frontends.- Mixed signal: Design issues.- Top-down design of mixed-signal circuits.- Computer aided design for integrated systems.- Mixed mode sigma-delta ADC design for high-quality audio.- Mixed mode telecom design.- III: PLL’s and Synthesizers.- On placing multiple inductor-based VCOs on the same mixed-signal substrate.- Fully integrated CMOS frequency synthesizers for wireless communications.- Design and optimization of RFCMOS-circuits for integrated PLL’s and synthesizers.- Frequency synthesis for integrated transceivers.- PLL frequency synthesizers: Phase noise issues and wide-band loops.- Low-power circuits for RF-frequency synthesizers in the low GHz range.

Recenzii

`The authors are to be complimented for collecting, into a single reference, a lot of interesting information related to the above mentioned topics, particularly useful for data-acquisition system designers, RF engineers, and others.'
Microelectronics Journal 29 (1998) 1039-1046

Descriere

Descriere de la o altă ediție sau format:
The realization of signal sampling and quantization at high sample rates with low power dissipation is an important goal in many applications, includ­ ing portable video devices such as camcorders, personal communication devices such as wireless LAN transceivers, in the read channels of magnetic storage devices using digital data detection, and many others. This paper describes architecture and circuit approaches for the design of high-speed, low-power pipeline analog-to-digital converters in CMOS. Here the term high speed is taken to imply sampling rates above 1 Mhz. In the first section the dif­ ferent conversion techniques applicable in this range of sample rates is dis­ cussed. Following that the particular problems associated with power minimization in video-rate pipeline ADCs is discussed. These include optimi­ zation of capacitor sizes, design of low-voltage transmission gates, and opti­ mization of switched capacitor gain blocks and operational amplifiers for minimum power dissipation. As an example of the application of these tech­ niques, the design of a power-optimized lO-bit pipeline AID converter (ADC) that achieves =1. 67 mW per MS/s of sampling rate from 1 MS/s to 20 MS/s is described. 2. Techniques for CMOS Video-Rate AID Conversion Analog-to-digital conversion techniques can be categorized in many ways. One convenient means of comparing techniques is to examine the number of "analog clock cycles" required to produce one effective output sample of the signal being quantized.