Analog Circuit Design: Low-Noise, Low-Power, Low-Voltage; Mixed-Mode Design with CAD Tools; Voltage, Current and Time References
Editat de Johan Huijsing, Rudy J. van de Plassche, Willy M.C. Sansenen Limba Engleză Hardback – 31 dec 1995
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Specificații
ISBN-13: 9780792396598
ISBN-10: 0792396596
Pagini: 422
Ilustrații: VIII, 422 p.
Dimensiuni: 155 x 235 x 28 mm
Greutate: 0.73 kg
Ediția:1996
Editura: Springer Us
Colecția Springer
Locul publicării:New York, NY, United States
ISBN-10: 0792396596
Pagini: 422
Ilustrații: VIII, 422 p.
Dimensiuni: 155 x 235 x 28 mm
Greutate: 0.73 kg
Ediția:1996
Editura: Springer Us
Colecția Springer
Locul publicării:New York, NY, United States
Public țintă
ResearchCuprins
I: Low-Noise, Low-Power, Low-Voltage Introduction.- Low-Noise HF Amplifiers.- Low-Noise, Low-Voltage, Low-Power IF Gain Controlled Amplifiers for Wireless Communication.- Autozeroing and Correlated Double Sampling Techniques.- Low-Noise Oscillators.- Design of High-Speed Low-Power Sample-and-Hold Amplifiers for Low-Voltage Applications.- Low Power Folding A/D Converters.- II: Mixed-Mode Design with CAD Tools Introduction.- Synthesis and Layout for Analog and Mixed-Signal ICs in the ACACIA System.- CAD Simulation for Mixed Signal Design.- Mixed Mode Simulation: Practical Problems and Solutions in UNICAD.- Mixed-Mode Design: Experiences with Multi-Level Macromodeling.- Behavioral Modeling and Simulation of Mixed-Signal Circuits.- Computer-Aided Testability Analysis for Analog Circuits.- III: Voltage, Current and Time References Introduction.- Concepts for Bandgap References and Voltage Measurement Systems.- Monolithic Voltage and Current References: Theme and Variations.- Integrated Current and Time References.- Crystal Oscillators.- Low-Phase-Noise Gigahertz Voltage-Controlled Oscillators in CMOS.- A2 GHZ Low-Power Frequency Synthesizer.
Recenzii
`The authors are to be complimented for collecting, into a single reference, a lot of interesting information related to the above mentioned topics, particularly useful for data-acquisition system designers, RF engineers, and others.'
Microelectronics Journal 29 (1998) 1039-1046
Microelectronics Journal 29 (1998) 1039-1046
Descriere
Descriere de la o altă ediție sau format:
The realization of signal sampling and quantization at high sample rates with low power dissipation is an important goal in many applications, includ ing portable video devices such as camcorders, personal communication devices such as wireless LAN transceivers, in the read channels of magnetic storage devices using digital data detection, and many others. This paper describes architecture and circuit approaches for the design of high-speed, low-power pipeline analog-to-digital converters in CMOS. Here the term high speed is taken to imply sampling rates above 1 Mhz. In the first section the dif ferent conversion techniques applicable in this range of sample rates is dis cussed. Following that the particular problems associated with power minimization in video-rate pipeline ADCs is discussed. These include optimi zation of capacitor sizes, design of low-voltage transmission gates, and opti mization of switched capacitor gain blocks and operational amplifiers for minimum power dissipation. As an example of the application of these tech niques, the design of a power-optimized lO-bit pipeline AID converter (ADC) that achieves =1. 67 mW per MS/s of sampling rate from 1 MS/s to 20 MS/s is described. 2. Techniques for CMOS Video-Rate AID Conversion Analog-to-digital conversion techniques can be categorized in many ways. One convenient means of comparing techniques is to examine the number of "analog clock cycles" required to produce one effective output sample of the signal being quantized.
The realization of signal sampling and quantization at high sample rates with low power dissipation is an important goal in many applications, includ ing portable video devices such as camcorders, personal communication devices such as wireless LAN transceivers, in the read channels of magnetic storage devices using digital data detection, and many others. This paper describes architecture and circuit approaches for the design of high-speed, low-power pipeline analog-to-digital converters in CMOS. Here the term high speed is taken to imply sampling rates above 1 Mhz. In the first section the dif ferent conversion techniques applicable in this range of sample rates is dis cussed. Following that the particular problems associated with power minimization in video-rate pipeline ADCs is discussed. These include optimi zation of capacitor sizes, design of low-voltage transmission gates, and opti mization of switched capacitor gain blocks and operational amplifiers for minimum power dissipation. As an example of the application of these tech niques, the design of a power-optimized lO-bit pipeline AID converter (ADC) that achieves =1. 67 mW per MS/s of sampling rate from 1 MS/s to 20 MS/s is described. 2. Techniques for CMOS Video-Rate AID Conversion Analog-to-digital conversion techniques can be categorized in many ways. One convenient means of comparing techniques is to examine the number of "analog clock cycles" required to produce one effective output sample of the signal being quantized.