Analog Circuit Design: MOST RF Circuits, Sigma-Delta Converters and Translinear Circuits
Editat de Willy M.C. Sansen, Johan Huijsing, Rudy J. van de Plasscheen Limba Engleză Hardback – 31 oct 1996
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Specificații
ISBN-13: 9780792397762
ISBN-10: 0792397762
Pagini: 410
Ilustrații: VIII, 410 p.
Dimensiuni: 156 x 234 x 29 mm
Greutate: 0.73 kg
Ediția:1996
Editura: Springer Us
Colecția Springer
Locul publicării:New York, NY, United States
ISBN-10: 0792397762
Pagini: 410
Ilustrații: VIII, 410 p.
Dimensiuni: 156 x 234 x 29 mm
Greutate: 0.73 kg
Ediția:1996
Editura: Springer Us
Colecția Springer
Locul publicării:New York, NY, United States
Public țintă
ResearchCuprins
I: MOST RF Circuit Design.- RF modelling of MOSFETs.- High Integration CMOS RF Transceivers.- 2 GHz RF Circuits in BiCMOS Process.- RF CMOS Design, Some Untold Pitfalls.- Silicon Integration for Digital Cellular Communication.- A Monolithic 900 Mhz Spread-Spectrum Wireless Transceiver in 1-µm CMOS.- II: Bandpass Delta-Sigma and other Data Converters.- Low-Power CMOS ?? modulators for speech coding.- Passive Sigma-Delta Modulators with Built-in Passive Mixers for Mobile Communications.- Design of Continuous Time Bandpass ?? modulators in CMOS.- Bandpass Delta-Sigma Converters in IF Receivers.- Design and Optimization of a Third-Order Switched-capacitor Reconstruction Filters for Sigma-Delta DAC’s.- Tools For Automated Design of ?? Modulators.- III: Translinear Circuits.- Aspects of Translinear Amplifier Design.- Variable-Gain, Variable-Transconductance, and Multiplication Techniques: A Survey.- CMOS Translinear Circuits.- Design of MOS Translinear Circuits Operating in Strong Inversion.- Translinear Circuits in Low-Voltage Operational Amplifiers.- Low-Voltage Continuous-Time Filters.
Recenzii
`The authors are to be complimented for collecting, into a single reference, a lot of interesting information related to the above mentioned topics, particularly useful for data-acquisition system designers, RF engineers, and others.'
Microelectronics Journal 29 (1998) 1039-1046
Microelectronics Journal 29 (1998) 1039-1046
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The realization of signal sampling and quantization at high sample rates with low power dissipation is an important goal in many applications, includ ing portable video devices such as camcorders, personal communication devices such as wireless LAN transceivers, in the read channels of magnetic storage devices using digital data detection, and many others. This paper describes architecture and circuit approaches for the design of high-speed, low-power pipeline analog-to-digital converters in CMOS. Here the term high speed is taken to imply sampling rates above 1 Mhz. In the first section the dif ferent conversion techniques applicable in this range of sample rates is dis cussed. Following that the particular problems associated with power minimization in video-rate pipeline ADCs is discussed. These include optimi zation of capacitor sizes, design of low-voltage transmission gates, and opti mization of switched capacitor gain blocks and operational amplifiers for minimum power dissipation. As an example of the application of these tech niques, the design of a power-optimized lO-bit pipeline AID converter (ADC) that achieves =1. 67 mW per MS/s of sampling rate from 1 MS/s to 20 MS/s is described. 2. Techniques for CMOS Video-Rate AID Conversion Analog-to-digital conversion techniques can be categorized in many ways. One convenient means of comparing techniques is to examine the number of "analog clock cycles" required to produce one effective output sample of the signal being quantized.
The realization of signal sampling and quantization at high sample rates with low power dissipation is an important goal in many applications, includ ing portable video devices such as camcorders, personal communication devices such as wireless LAN transceivers, in the read channels of magnetic storage devices using digital data detection, and many others. This paper describes architecture and circuit approaches for the design of high-speed, low-power pipeline analog-to-digital converters in CMOS. Here the term high speed is taken to imply sampling rates above 1 Mhz. In the first section the dif ferent conversion techniques applicable in this range of sample rates is dis cussed. Following that the particular problems associated with power minimization in video-rate pipeline ADCs is discussed. These include optimi zation of capacitor sizes, design of low-voltage transmission gates, and opti mization of switched capacitor gain blocks and operational amplifiers for minimum power dissipation. As an example of the application of these tech niques, the design of a power-optimized lO-bit pipeline AID converter (ADC) that achieves =1. 67 mW per MS/s of sampling rate from 1 MS/s to 20 MS/s is described. 2. Techniques for CMOS Video-Rate AID Conversion Analog-to-digital conversion techniques can be categorized in many ways. One convenient means of comparing techniques is to examine the number of "analog clock cycles" required to produce one effective output sample of the signal being quantized.