The Verilog PLI Handbook: A User’s Guide and Comprehensive Reference on the Verilog Programming Language Interface
Autor Stuart Sutherlanden Limba Engleză Paperback – 5 noi 2012
Intended audience: this book is written for digital design engineers with a background in the Verilog Hardware Description Language and a fundamental knowledge of the C programming language. It is expected that thereader:
- Has a basic knowledge of hardware engineering, specifically digital design of ASIC and FPGA technologies.
- Is familiar with the Verilog Hardware Description Language (HDL), and can write models of hardware circuits in Verilog, can write simulation test fixtures in Verilog, and can run at least one Verilog logic simulator.
- Knows basic C-language programming, including the use of functions, pointers, structures and file I/O. Explanations of the concepts and terminology of digital
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Specificații
ISBN-13: 9781461372790
ISBN-10: 1461372798
Pagini: 812
Ilustrații: XXIII, 785 p.
Dimensiuni: 155 x 235 x 43 mm
Greutate: 1.12 kg
Ediția:Softcover reprint of the original 1st ed. 1999
Editura: Springer Us
Colecția Springer
Locul publicării:New York, NY, United States
ISBN-10: 1461372798
Pagini: 812
Ilustrații: XXIII, 785 p.
Dimensiuni: 155 x 235 x 43 mm
Greutate: 1.12 kg
Ediția:Softcover reprint of the original 1st ed. 1999
Editura: Springer Us
Colecția Springer
Locul publicării:New York, NY, United States
Public țintă
ResearchCuprins
Introduction: The VPI and TF/ACC Parts of the Verilog PLI Standard.- 1: Creating PLI Applications Using VPI Routines.- 2: Interfacing VPI PLI Applications to Verilog Simulators.- 3: How to Use the VPI Routines.- 4: Details about the VPI Routine Library.- 5: Reading and Modifying Values Using VPI Routines.- 6: Synchronizing to Verilog Simulations Using VPI Callbacks.- 7: Interfacing to C Models Using VPI Routines.- 8: Creating PLI Applications Using TF and ACC Routines.- 9: Interfacing TF/ACC PLI Applications to Verilog Simulators.- 10: How to Use the TF Routines.- 11: Reading and Writing Values Using TF Routines.- 12: Synchronizing to Verilog Simulations Using Misctf Routines.- 13: Interfacing to C Models Using TF Routines.- 14: How to Use the ACC Routines.- 15: Details on the ACC Routine Library.- 16: Reading and Modifying Values Using ACC Routines.- 17: Synchronizing to Simulations Using the Value Change Link.- 18: Interfacing to C Models Using ACC Routines.- Appendices.- Appendix A:Linking PLI Applications to Verilog Simulators.- A.1 The PLI Interface Mechanism.- A.2 Linking PLI app’s to the Cadence Verilog-XL simulator.- A.3 Linking to NC-Verilog from Cadence Design Systems, Inc..- A.4 Linking PLI applications to the Model Technology ModelSim simulator.- A.5 Linking PLI applications to the Avant! Polaris simulator.- A.6 Linking to Silos III from Simucad, Inc..- A.7 Linking to VCS from Synopsys, Inc.- A.8 Linking to VeriBest from VeriBest, Inc.- A.9 Summary.- Appendix B: The IEEE 1364–1995 VPI Routine Library.- B.1 VPI Objects Relationships.- B.2 VPI routine definitions (listed alphabetically).- Appendix C: The IEEE 1364–1995 TF Routine Library.- C.1 TF routine definitions (listed alphabetically).- Appendix D: The IEEE 1364–1995 ACC Routine Library.- D.1 ACC Objects Relationships.- D.2 ACC routine definitions (listed alphabetically).
Notă biografică
Mr. Stuart Sutherland is a member of the IEEE Verilog standards committee, where he is co-chair of the PLI standards task force and technical editor for the PLI sections of the IEEE 1364 Verilog Language Reference Manual.
Mr. Sutherland has more than 14 years of experience in hardware design and over ten years of experience with Verilog. He is the founder of Sutherland HDL Inc., located in Portland Oregon. Sutherland HDL provides expert Verilog HDL and Verilog PLI design services, including training, modeling, design verification and software tool evaluation. Verilog training is one of the specialties of Sutherland HDL. Prior to founding Sutherland HDL in 1992, Mr. Sutherland was as an engineer at Sanders Display Products Division in New Hampshire, where he worked on high speed graphics systems for the defense industry. In 1988, he became a senior applications engineer for Gateway Design Automation, the founding company of Verilog. AtGateway, which was acquired by Cadence Design Systems in 1989, Mr. Sutherland specialized in training and support for logic simulation, timing analysis, fault simulation, and the Verilog PLI. Mr. Sutherland has also worked closely with several EDA vendors to specify, test and bring to market Verilog simulation products. Mr. Sutherland holds a Bachelor of Science in Computer Science, with an emphasis in Electronic Engineering Technology, from Weber State University (Ogden, Utah) and Franklin Pierce College (Nashua, New Hampshire). He has taught Verilog engineering courses at the University of California, Santa Cruz (Santa Clara extension), and has authored the popular "Verilog HDL Quick Reference Guide" and "Verilog PU Quick Reference Guide". He has presented tutorials and papers at the International Verilog Conference and at the International Cadence User's Group Conference, and has won awards for best speaker and best tutorial.
Mr. Sutherland has more than 14 years of experience in hardware design and over ten years of experience with Verilog. He is the founder of Sutherland HDL Inc., located in Portland Oregon. Sutherland HDL provides expert Verilog HDL and Verilog PLI design services, including training, modeling, design verification and software tool evaluation. Verilog training is one of the specialties of Sutherland HDL. Prior to founding Sutherland HDL in 1992, Mr. Sutherland was as an engineer at Sanders Display Products Division in New Hampshire, where he worked on high speed graphics systems for the defense industry. In 1988, he became a senior applications engineer for Gateway Design Automation, the founding company of Verilog. AtGateway, which was acquired by Cadence Design Systems in 1989, Mr. Sutherland specialized in training and support for logic simulation, timing analysis, fault simulation, and the Verilog PLI. Mr. Sutherland has also worked closely with several EDA vendors to specify, test and bring to market Verilog simulation products. Mr. Sutherland holds a Bachelor of Science in Computer Science, with an emphasis in Electronic Engineering Technology, from Weber State University (Ogden, Utah) and Franklin Pierce College (Nashua, New Hampshire). He has taught Verilog engineering courses at the University of California, Santa Cruz (Santa Clara extension), and has authored the popular "Verilog HDL Quick Reference Guide" and "Verilog PU Quick Reference Guide". He has presented tutorials and papers at the International Verilog Conference and at the International Cadence User's Group Conference, and has won awards for best speaker and best tutorial.
Recenzii
"The Verilog PLI Handbook is the best book written about the PLI. Use it once, and it will pay for itself by saving you a great deal of time. The book brings clarity to the Verilog Programming Language Interface. The descriptions and extensive examples shed new light on the many dark corners of the PLI. Stuart Sutherland has produced the definitive guide, covering all versions and uses for the PLI. I recommend this book to all Verilog users who want to learn about the PLI."
(Chris Spear, Verification Consultant, Synopsys, Inc.)
(Chris Spear, Verification Consultant, Synopsys, Inc.)