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Synthesizable VHDL Design for FPGAs

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en Limba Engleză Carte Hardback – 31 Oct 2013
The methodology described in this book is the result of many years of research experience in the field of synthesizable VHDL design targeting FPGA based platforms. VHDL was first conceived as a documentation language for ASIC designs. Afterwards, the language was used for the behavioral simulation of ASICs, and also as a design input for synthesis tools. VHDL is a rich language, but just a small subset of it can be used to write synthesizable code, from which a physical circuit can be obtained. Usually VHDL books describe both, synthesis and simulation aspects of the language, but in this book the reader is conducted just through the features acceptable by synthesis tools. The book introduces the subjects in a gradual and concise way, providing just enough information for the reader to develop their synthesizable digital systems in VHDL. The examples in the book were planned targeting an FPGA platform widely used around the world.
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Specificații

ISBN-13: 9783319025469
ISBN-10: 3319025465
Pagini: 200
Ilustrații: 174 illus., 174 schwarz-weiße Abbildungen
Dimensiuni: 155 x 235 x 17 mm
Greutate: 0.43 kg
Ediția: 2014
Editura: Springer
Colecția Springer
Locul publicării: Cham, Switzerland

Public țintă

Professional/practitioner

Cuprins

Digital Systems, FPGAs and the Design Flow.- HDL Based Designs.- Hierarchical Design.- Multiplexer and Demultiplexer.- Code Converters.- Sequential Circuits, Latches and Flip-Flops.- Synthesis of Finite State Machines.- Finite State Machines as Control Modules.- Processes in Details.- Arithmetic Circuits.- VHDL Design Examples for FPGA Synthesis.

Notă biografică

Dr. Eduardo Bezerra is a Researcher and Lecturer of Computer Engineering at Universidade Federal de Santa Catarina (UFSC), where he is with the Department of Electrical Engineering since 2010. He received his Ph.D. in Computer Engineering from the University of Sussex (Space Science Centre), England, UK, in 2002. His research interests are in the areas of embedded systems, computer architecture, reconfigurable systems (FPGAs), space applications, software & hardware testing, fault tolerance and microprocessor applications.
Djones Lettnin has Master´s in Electric Engineering at Catholic University of Rio Grande do Sul (2004), Brazil, and Sc.D. in Computer Engineering at the Eberhard Karls University of Tübingen (2009), Germany. In August 2011 he became Professor at Federal University of Santa Catarina, Brazil. Since August 2012 he is first coordinator of the Cadence Academic Network in Latin America. His main interests are in design and functional verification of hardware and embedded software with main focus on: modeling of embedded systems, digital design, verification based on assertions, semiformal and formal verification using model checking.


Textul de pe ultima copertă

This book provides a gradual description of very-high-speed integrated circuits hardware description language (VHDL), targeting the design of digital systems to be implemented in field-programmable gate array (FPGA) platforms. It is organized in a very didactic way. The adopted methodolgy was matured over 20 years of teaching experience in the subject. The examples in the book were planned targeting two FPGA platforms, one used widely around the world and the other one developed by a Brazilian company.

Caracteristici

Introduces the subjects in a very concise format, providing just enough information for the reader to develop their first digital systems in VHDL
Book content based on 20 years of experience teaching the subject in undergraduate and graduate courses
Provides a design kit