Switch-Level Timing Simulation of Mos VLSI Circuits
Autor Vasant B Rao, David V Overhauser, Timothy N Trick, Ibrahim N Hajjen Limba Engleză Hardback – 30 noi 1988
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Specificații
ISBN-13: 9780898383027
ISBN-10: 0898383021
Pagini: 210
Ilustrații: XII, 210 p.
Dimensiuni: 160 x 241 x 17 mm
Greutate: 0.5 kg
Ediția:1989 edition
Editura: Springer Us
Locul publicării:New York, NY, United States
ISBN-10: 0898383021
Pagini: 210
Ilustrații: XII, 210 p.
Dimensiuni: 160 x 241 x 17 mm
Greutate: 0.5 kg
Ediția:1989 edition
Editura: Springer Us
Locul publicării:New York, NY, United States
Public țintă
ResearchCuprins
1. Introduction.- 2. Overview of Simulation Techniques.- 2.1 Analog vs Digital Simulation.- 2.2 Gate-Level Simulation.- 2.3 Switch-Level Logic Simulation.- 2.4 Mixed-Mode or Hybrid Simulation.- 2.5 Switch-Level Timing Simulation.- 3. Mos Network Partitioning and Ordering.- 3.1 MOS Network Components and Models.- 3.2 Partitioning the MOS Network into Blocks.- 3.3* Partitioning into Driver and Pass Transistors.- 3.4 Ordering of Partitioned Blocks.- 3.5 Conclusions.- 4. Switch-Level Timing Simulation.- 4.1 Overview.- 4.2 Waveform Representation.- 4.3 Simulation Algorithm.- 4.4 Deriving Inverter Voltage Equations.- 4.5 Determining the dc Output Voltage.- 4.6 Mapping Complex Blocks to Primitives.- 4.7 Parasitics.- 4.8 Sample Subcircuit Processing.- 5. Simulating Strongly Connected Components.- 5.1 Waveform Relaxation vs Time-point Relaxation.- 5.2 Dynamic Windowing.- 6. Performance of Idsim2.- References.- About The Authors.