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Power-Aware Computer Systems

Editat de Babak Falsafi, T. N. Vijaykumar
en Limba Engleză Paperback – 7 apr 2003
Welcome to the proceedings of the 3rd Power-Aware Computer Systems (PACS 2003) Workshop held in conjunction with the 36th Annual International Symposium on Microarchitecture (MICRO-36). The increase in power and - ergy dissipation in computer systems has begun to limit performance and has also resulted in higher cost and lower reliability. The increase also implies - ducedbatterylifeinportablesystems.Becauseofthemagnitudeoftheproblem, alllevelsofcomputersystems,includingcircuits,architectures,andsoftware,are being employed to address power and energy issues. PACS 2003 was the third workshop in its series to explore power- and energy-awareness at all levels of computer systems and brought together experts from academia and industry. These proceedings include 14 research papers, selected from 43 submissions, spanningawidespectrumofareasinpower-awaresystems.Wehavegrouped the papers into the following categories: (1) compilers, (2) embedded systems, (3) microarchitectures, and (4) cache and memory systems. The ?rst paper on compiler techniques proposes pointer reuse analysis that is biased by runtime information (i.e., the targets of pointers are determined based on the likelihood of their occurrence at runtime) to map accesses to ener- e?cient memory access paths (e.g., avoid tag match). Another paper proposes compiling multiple programs together so that disk accesses across the programs can be synchronized to achieve longer sleep times in disks than if the programs are optimized separately.
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Specificații

ISBN-13: 9783540010289
ISBN-10: 3540010289
Pagini: 232
Ilustrații: X, 226 p.
Dimensiuni: 155 x 235 x 13 mm
Greutate: 0.36 kg
Ediția:2003
Editura: Springer
Locul publicării:Berlin, Heidelberg, Germany

Public țintă

Research

Cuprins

Power-Aware Architecture/Microarchitecture.- Early-Stage Definition of LPX: A Low Power Issue-Execute Processor.- Dynamic Tag-Check Omission: A Low Power Instruction Cache Architecture Exploiting Execution Footprints.- A Hardware Architecture for Dynamic Performance and Energy Adaptation.- Multi-Processor Computer System Having Low Power Consumption.- Power-Aware Real-Time Systems.- An Integrated Heuristic Approach to Power-Aware Real-Time Scheduling.- Power-Aware Task Motion for Enhancing Dynamic Range of Embedded Systems with Renewable Energy Sources.- A Low-Power Content-Adaptive Texture Mapping Architecture for Real-Time 3D Graphics.- Power Modeling and Monitoring.- Energy-Driven Statistical Sampling: Detecting Software Hotspots.- Modeling of DRAM Power Control Policies Using Deterministic and Stochastic Petri Nets.- SimDVS: An Integrated Simulation Environment for Performance Evaluation of Dynamic Voltage Scaling Algorithms.- Power-Aware OS and Compilers.- Application-Supported Device Management for Energy and Performance.- Energy-Efficient Server Clusters.- Single Region vs. Multiple Regions: A Comparison of Different Compiler-Directed Dynamic Voltage Scheduling Approaches.