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Massive MIMO Detection Algorithm and VLSI Architecture de Leibo Liu

Massive MIMO Detection Algorithm and VLSI Architecture

Autor Leibo Liu, Guiqiang Peng, Shaojun Wei
en Limba Engleză Hardback – 5 mar 2019
This book introduces readers to a reconfigurable chip architecture for future wireless communication systems, such as 5G and beyond. The proposed architecture perfectly meets the demands for future mobile communication solutions to support different standards, algorithms, and antenna sizes, and to accommodate the evolution of standards and algorithms. It employs massive MIMO detection algorithms, which combine the advantages of low complexity and high parallelism, and can fully meet the requirements for detection accuracy. Further, the architecture is implemented using ASIC, which offers high energy efficiency, high area efficiency and low detection error.
After introducing massive MIMO detection algorithms and circuit architectures, the book describes the ASIC implementation for verifying the massive MIMO detection. In turn, it provides detailed information on the proposed reconfigurable architecture: the data path and configuration path for massive MIMO detection algorithms, including the processing unit, interconnections, storage mechanism, configuration information format, and configuration method. 
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Specificații

ISBN-13: 9789811363610
ISBN-10: 9811363617
Pagini: 352
Ilustrații: XVI, 336 p. 186 illus., 120 illus. in color.
Dimensiuni: 160 x 241 x 25 mm
Greutate: 0.64 kg
Ediția:1st edition 2019
Editura: Springer
Locul publicării:Singapore, Singapore

Cuprins

Chapter 1 Introduction.- Chapter 2 Linear Massive MIMO Detection Algorithm.- Chapter 3 Architecture of Linear Massive MIMO Detection.- Chapter 4 Nonlinear Massive MIMO Signal Detection Algorithm.- Chapter 5 Hardware Architecture for Nonlinear Massive MIMO Detection.- Chapter 6 Dynamic Reconfigurable Chips for Massive MIMO Detection.- Chapter 7 Prospect of the VLSI Architecture for Massive MIMO Detection.

Notă biografică

Shaojun Wei (Fellow, IEEE) received the Ph.D. degree from the La Faculté Polytechnique de Mons, Mons, Belgium, in 1991. He is a professor at the School of Integrated Circuits, Tsinghua University, Beijing, China, His main research interests include reconfigurable computing VLSI system-on-chip (SoC) design, electronic design automation (EDA) methodology and application specific integrated circuit (ASIC) design for communications. Prof. Wei has published more than 230 peer-reviewed journal and conference papers, 9 books/book chapters with one of them being the first book on Reconfigurable Computing in China and nearly 100 international patents with several winning national awards. The main contributions of Prof. Wei are acknowledged by (1) dynamically reconfigurable computing pattern, (2) reconfigurable cell array architecture supporting highly efficient implementation of control-intensive applications, (3) configuration information mapping mechanism improving performance and power consumption. These technologies found applications in multimedia, cryptographic and neural processors, as well as processors for data centers. They not only laid the ground for software defined chips but were also highly appreciated by industry leaders such as Intel. Since 2009, Intel has carried out large projects with Prof. Wei's team for collaborative research and development. Prof. Wei has been coordinating the strategic plan for the semiconductor development in China as the leading expert of the "863 program" since 2000 and as the chief scientist of "National Key Projects of Science and Technology" for more than 10 years. His enormous contributions to IC design during the past 20 years have earned him the IEEE CAS Industrial Pioneer Award. Leibo Liu received B.S. and Ph.D. from Tsinghua University in 1999 and 2004, respectively. He is a tenured professor of the School of Integrated Circuits at Tsinghua University. His research interests include reconfigurable computing, hardware security and cryptographic engines. Jianfeng Zhu received the B.S. and Ph.D. degrees in electronic science and technology from Tsinghua University, Beijing, China, in 2008 and 2015, respectively. He is currently with School of Integrated Circuits, Tsinghua University. His current research interests include software defined chips, the architecture and compilation of CGRA, hardware security and low-power design. Chenchen Deng received the B.S. in Electronic Engineering from Beijing University of Posts and Telecommunications, China, in 2007 and the D.Phil. in Engineering Science from University of Oxford, UK, in 2012. She now works as an assistant research fellow at Beijing National Research Center for Information Science and Technology, Tsinghua University, Beijing. Her current research interests include software defined chips, reconfigurable computing, energy-efficient computing systems and design methods for hardware security.

Textul de pe ultima copertă

This book introduces readers to a reconfigurable chip architecture for future wireless communication systems, such as 5G and beyond. The proposed architecture perfectly meets the demands for future mobile communication solutions to support different standards, algorithms, and antenna sizes, and to accommodate the evolution of standards and algorithms. It employs massive MIMO detection algorithms, which combine the advantages of low complexity and high parallelism, and can fully meet the requirements for detection accuracy. Further, the architecture is implemented using ASIC, which offers high energy efficiency, high area efficiency and low detection error.
After introducing massive MIMO detection algorithms and circuit architectures, the book describes the ASIC implementation for verifying the massive MIMO detection. In turn, it provides detailed information on the proposed reconfigurable architecture: the data path and configuration path for massive MIMO detection algorithms, including the processing unit, interconnections, storage mechanism, configuration information format, and configuration method. 

Caracteristici

Present a dynamic and reconfigurable architecture for future wireless communication systems, e.g. 5G and beyond Introduces massive multiple-input multiple-output (MIMO) technology, which can improve network capacity, enhance network robustness and reduce communication delays Reviews various implementations of the architecture and explains the ASIC-based approach, which offers high energy efficiency, high area efficiency and low detection error