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Low Power Networks-On-Chip de Cristina Silvano

Low Power Networks-On-Chip

Editat de Cristina Silvano, Marcello Lajolo, Gianluca Palermo
en Limba Engleză Hardback – 6 oct 2010
In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities. This book offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures.
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Specificații

ISBN-13: 9781441969101
ISBN-10: 1441969101
Pagini: 287
Ilustrații: XIX, 287 p.
Dimensiuni: 167 x 244 x 28 mm
Greutate: 0.62 kg
Ediția:2011
Editura: Springer Us
Locul publicării:New York, NY, United States

Public țintă

Research

Cuprins

Network-on-Chip Power Estimation.- Timing.- synchronous/asynchronous communication.- Network-on-Chip link design.- Topology exploration.- Network-on-Chip support for CMP/MPSoCs.- Network design for 3D stacked logic and memory.- Beyond the wired Network-on-Chip.

Textul de pe ultima copertă

Low Power Networks-on-Chip Edited by: (editors)Cristina Silvano Marcello LajoloGianluca Palermo In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities, since power and energy issuesstill represent one of the limiting factors in integrating multi- and many-coreson a single chip. This book covers power and energy aware design techniques from several perspectives and abstraction levels and offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures. •Describes the most important design techniques that were invented, proposed, and applied to reduce both dynamic power and static power dissipation in networks-on-chip based architectures;•Applies state-of-the-art, low-power design techniques to the design of Networks-on-Chip, to demonstrate methodology for design of high-speed, low-power interconnect; •Offers a single source reference to the latest research, otherwise available only in disparate journals and conference proceedings.