Finite State Machine Logic Synthesis for Complex Programmable Logic Devices
Autor Robert Czerwinski, Dariusz Kaniaen Limba Engleză Hardback – 12 ian 2013
Logic synthesis and optimization methods dedicated for PAL-based structures are proposed. The methods strive to find the optimum fit for the combinational logic and finite state machines to the structure of the logic device and aim at area and speed optimization. The theoretical background and complete strategies are richly illustrated with examples and figures.
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| Springer Berlin, Heidelberg – 25 iun 2015 | 596.91 lei 38-44 zile | |
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| Springer – 12 ian 2013 | 609.06 lei 38-44 zile |
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Specificații
ISBN-13: 9783642361654
ISBN-10: 364236165X
Pagini: 188
Ilustrații: XV, 172 p.
Dimensiuni: 160 x 241 x 15 mm
Greutate: 0.45 kg
Ediția:2013
Editura: Springer
Locul publicării:Berlin, Heidelberg, Germany
ISBN-10: 364236165X
Pagini: 188
Ilustrații: XV, 172 p.
Dimensiuni: 160 x 241 x 15 mm
Greutate: 0.45 kg
Ediția:2013
Editura: Springer
Locul publicării:Berlin, Heidelberg, Germany
Public țintă
ResearchCuprins
Introduction.- Definitions and Basic Properties.- Synthesis of FSMs.- State Assignment Algorithms.- Theoretical Background of Technology-Dependent Optimization.- The Algorithm of Area Optimization Based on Graphs of Outputs.- Conclusions.- Output File Format.- Conclusion.
Textul de pe ultima copertă
This book is a monograph devoted to logic synthesis and optimization for CPLDs. CPLDs' macrocell can also be interpreted as programmable AND-fixed OR structure, well known as PAL-based structure. The question is: what should be done when the number of implicants representing function exceeds the number of product terms available in a logic block. The answer is ... in the book.
Logic synthesis and optimization methods dedicated for PAL-based structures are proposed. The methods strive to find the optimum fit for the combinational logic and finite state machines to the structure of the logic device and aim at area and speed optimization. The theoretical background and complete strategies are richly illustrated with examples and figures.
Logic synthesis and optimization methods dedicated for PAL-based structures are proposed. The methods strive to find the optimum fit for the combinational logic and finite state machines to the structure of the logic device and aim at area and speed optimization. The theoretical background and complete strategies are richly illustrated with examples and figures.
Caracteristici
Devoted to logic synthesis and optimization for Complex Programmable Logic Devices Presents logic synthesis and optimization methods dedicated for Programmable Array Logic –based structures Written by leading experts in the field