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Esd de Steven H Voldman

Esd

Autor Steven H Voldman
en Limba Engleză Hardback – sep 2009

Metodologia abordată în această lucrare pune accent pe integrarea protecției împotriva descărcărilor electrostatice încă din faza de proiectare a arhitecturii schematice și a layout-ului circuitelor analogice. Ne-a atras atenția modul în care Steven H Voldman reușește să echilibreze cerințele stricte de performanță ale circuitelor de putere cu necesitatea unor structuri de protecție robuste. Suntem de părere că tranziția de la conceptele fundamentale de layout MOSFET, prezentate în primele capitole, către sinteza complexă a semnalelor mixte analog-digitale oferă o progresie logică, esențială pentru înțelegerea integrității semnalului în medii industriale. Spre deosebire de abordările care tratează ESD ca pe un element periferic, acest volum fundamentează o disciplină de sine stătătoare pentru designul analogic. Ca și Oleg Semenov în Esd Protection Device and Circuit Design for Advanced CMOS Technologies, autorul distilează experiență reală în principii acționabile, însă Voldman extinde spectrul tehnologic către zone specifice precum BCD și SOI. Structura tehnică este riguroasă: primele secțiuni se concentrează pe amplificatoare cu tranzistori și sarcini active, în timp ce partea a doua rezolvă provocările specifice pinilor de semnal și clemelor de putere (power clamps). În contextul operei sale, Esd completează viziunea sistemică începută în Esd Testing, mutând focusul de la validare la prevenție prin design. Dacă în Latchup autorul analiza mecanismele de eșec parazit, aici oferă soluții constructive pentru circuitele RF și analogice, unde liniaritatea și factorul de calitate sunt critice. Volumul include metodologii avansate de testare, precum TDR, asigurând un suport tehnic complet pentru inginerii care proiectează circuite integrate moderne.

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Specificații

ISBN-13: 9780470511374
ISBN-10: 0470511370
Pagini: 408
Dimensiuni: 177 x 252 x 27 mm
Greutate: 0.82 kg
Editura: Wiley
Locul publicării:Chichester, United Kingdom

Public țintă

Engineers and technicians,researchers and graduate students

De ce să citești această carte

Această lucrare este indispensabilă inginerilor de design analogic care trebuie să implementeze soluții de protecție ESD fără a compromite performanța circuitului. Cititorul câștigă o înțelegere profundă a interacțiunii dintre layout și fiabilitate, primind instrumente practice pentru tehnologii variate (CMOS, SOI, LDMOS). Este un ghid tehnic ce transformă teoria fizicii descărcărilor în reguli de design aplicabile imediat în fluxul de producție al circuitelor integrate.

Despre autor

Steven H. Voldman este un expert recunoscut la nivel mondial în domeniul protecției împotriva descărcărilor electrostatice (ESD) și al fiabilității semiconductorilor. Cu o carieră marcată de numeroase brevete și publicații tehnice, el a contribuit semnificativ la standardizarea procedurilor de testare și design în cadrul industriei microelectronice. Lucrările sale, publicate frecvent de Wiley, sunt considerate referințe fundamentale atât în mediul academic, cât și în cel industrial. Expertiza sa acoperă o gamă largă de fenomene, de la latchup la efectele radiațiilor asupra circuitelor integrate, consolidându-i reputația de autoritate în ingineria fiabilității dispozitivelor semiconductoare moderne.

Notă biografică

Dr Steven H. Voldman received his B.S. in Engineering Science from the University of Buffalo (1979); M.S. EE (1981) and Electrical Engineer Degree (1982) from M.I.T; MS Engineering Physics (1986) and Ph.D EE (1991) from the University of Vermont under IBM's Resident Study Fellow Program. At M.I.T, he worked as a member of the M.I.T. Plasma Fusion Center, and the High Voltage Research Laboratory (HVRL). At IBM, as a reliability device engineer, his work include pioneering work in bipolar/ CMOS SRAM alpha particle and cosmic ray SER simulation, MOSFET gate-induced drain leakage (GIDL) mechanism, hot electron, epitaxy/well design, CMOS latchup, and ESD. Since 1986, he has been responsible for defining the IBM ESD/latchup strategy for CMOS, SOI, BiCMOS and RF CMOS and SiGe technologies. He has authored ESD and latchup publications in the area of MOSFET Scaling, device simulations, copper, low-k, MR heads, CMOS, SOI , Sage and SiGeC technology. Voldman served as SEMATECH ESD Working Group Chairman (1996-2000), ESD Association General Chairman and Board of Directors, International Reliability Physics (IRPS) ESD/Latchup Chairman, International Physical and Failure Analysis (IPFA) Symposium ESD Sub-Committee Chairman, ESD Association Standard Development Chairman on Transmission Line Pulse Testing, ESD Education Committee, and serves on the ISQED Committee, Taiwan ED Conference (T-ESDC) Technical Program Committee. Voldman has provided ESD lectures for universities (e.g. MIT Lecture Series, Taiwan National Chiao-Tung University, and Singapore Nanyang Technical University). He is a recipient of over 125 US patents, over 100 publications, and also provides talks on patenting, and invention. He has been featured in EE Times, Intellectual Property Law and Business and authored the first article on ESD phenomena for the October 2002 edition of Scientific American entitled Lightening Rods for Nanostructures, and Pour La Science, Le Scienze, and Swiat Nauk international editions. Dr. Voldman was recently accepted as the first IEEE Fellow for ESD phenomena in semiconductors for ' contributions to electrostatic discharge protection CMOS, SOI and SiGe technologies'.

Descriere

Provides a comprehensive analysis of ESD failure mechanisms over a wide range of semiconductor materials, devices, circuits and applications. Sets out methods for eliminating failure mechanisms through workable circuit solutions, including practical examples of failure defects.

Textul de pe ultima copertă

With the growth of high–speed telecommunications and wireless technology, it is becoming increasingly important for engineers to understand radio frequency (RF) applications and their sensitivity to electrostatic discharge (ESD) phenomena. This enables the development of ESD design methods for RF technology, leading to increased protection against electrical overstress (EOS) and ESD. ESD: RF Technology and Circuits:
  • Presents methods for co–synthesizisng ESD networks for RF applications to achieve improved performance and ESD protection of semiconductor chips;
  • discusses RF ESD design methods of capacitance load transformation, matching network co–synthesis, capacitance shunts, inductive shunts, impedance isolation, load cancellation methods, distributed loads, emitter degeneration, buffering and ballasting;
  • examines ESD protection and design of active and passive elements in RF complementary metal–oxide–semiconductor (CMOS), RF laterally–diffused metal oxide semiconductor (LDMOS), RF BiCMOS Silicon Germanium (SiGe), RF BiCMOS Silicon Germanium Carbon (SiGeC), and Gallim Arsenide technology;
  • gives information on RF ESD testing methodologies, RF degradation effects, and failure mechanisms for devices, circuits and systems;
  • highlights RF ESD mixed–signal design integration of digital, analog and RF circuitry;
  • sets out examples of RF ESD design computer aided design methodologies;
  • covers state–of–the–art RF ESD input circuits, as well as voltage–triggered to RC–triggered ESD power clamps networks in RF technologies, as well as off–chip protection concepts.
Following the authors series of books on ESD, this book will be a thorough overview of ESD in RF technology for RF semiconductor chip and ESD engineers. Device and circuit engineers working in the RF domain, and quality, reliability and failure analysis engineers will also find it a valuable reference in the rapidly growing are of RF ESD design. In addition, it will appeal to graduate students in RF microwave technology and RF circuit design.

Cuprins

Preface. Acknowledgments.
Chapter 1. RF DESIGN and ESD.
1.1 Fundamental Concepts of ESD design.
1.2 Fundamental Concepts of RF ESD Design.
1.3 Key RF ESD Contributions.
1.4 Key RF ESD Patents.
1.5 ESD Failure Mechanisms.
1.6 RF Basics.
1.7 Two–Port Network Parameters.
1.8. Stability: RF Design Stability and ESD.
1.9 Device Degradation and ESD Failure.
1.10 RF ESD Testing.
1.11 Time Domain Reflection (TDR) and Impedance Methodology.
1.12 Product Level ESD Test and RF Functional Parameter Failure.
1.13 Combined RF and ESD TLP Test Systems.
1.14 Closing Comments and Summary.
Problems.
References.
Chapter 2. RF ESD Design.
2.1 ESD Design Methods: Ideal ESD networks and RF.
2.2 RF ESD Design Methods: Linearity.
2.3 RF ESD Design: Passive Element Quality Factors and Figures of Merit.
2.4 RF ESD Design Methods: Method of Subsitution.
2.5 RF ESD Design Methods: Matching Networks and RF ESD Networks.
2.6 RF ESD Design Methods: Inductive Shunt.
2.7 RF ESD Design Methods: Cancellation Method.
2.8 RF ESD Design Methods: Impedance Isolation Technique Using.
2.9 RF ESD Design Methods: Lumped versus Distributed Loads.
2.10 ESD RF Design Synthesis and Floor Planning: RF, Analog, and Digital Integration.
2.11 ESD Circuits and RF Bond Pad Integration.
2.12 ESD Structures Under Wire Bond Pads.
2.13 Summary and Closing Comments.
Problems.
References.
Chapter 3. RF CMOS and ESD.
3.1 RF CMOS: ESD Device Comparisons.
3.2 Circular RF ESD Devices.
3.3 RF ESD Design ESD Wiring Design.
3.4 RF Passives: ESD and Schottky Barrier Diodes.
3.5 RF Passives: ESD and Inductors.
3.6 RF Passives: ESD and Capacitors.
3.7 Summary and Closing Comments.
Problems.
References.
Chapter 4. RF CMOS ESD Networks.
4.1 RF CMOS Input Circuits.
4.2 RF CMOS: Diode Inductor ESD Networks.
4.3 RF CMOS Impedance Isolation LC Resonator ESD Networks.
4.4 RF CMOS LNA ESD Design.
4.5 RF CMOS T–Coil Inductor ESD Input Network.
4.6 RF CMOS Distributed ESD Networks.
4.7 RF CMOS Distributed ESD Networks: Transmission Lines.
4.8 RF CMOS: ESD and RF LDMOS Power Technology.
4.9 RF CMOS ESD Power Clamps.
4.10 Summary and Closing Comments.
Problems.
References.
Chapter 5. Bipolar Physics.
5.1 Bipolar Device Physics.
5.2 Transistor Breakdown.
5.3 Kirk Effect.
5.4 Johnson Limit: Physical Limitations of the Transistor.
5.5 RF Instability: Emitter Collapse.
5.6 ESD RF Design Layout: Emitter, Base, and Collector Configurations.
5.7 ESD RF Design Layout: Utilization of a Second.
5.8 ESD RF Design Layout: Emitter Ballasting.
5.9 ESD RF Design Layout: Thermal Shunts and Thermal Lenses.
5.10 Base–Ballasting and RF Stability.
5.11 Summary and Closing Comments.
Problems.
References.
Chapter 6. Silicon Germanium and ESD.
6.1 Heterojunctions and Silicon Germanium Technology.
6.2 Silicon Germanium Physics.
6.3 Silicon Germanium Carbon.
6.4 Silicon Germanium ESD Measurements.
6.5. Silicon Germanium Carbon Collector Emitter ESD Measurements.
6.6 Silicon Germanium Transistor Emitter Base Design.
6.7 Field–Oxide (FOX) Isolation Defined Silicon Germanium.
6.8 Silicon Germanium HBT Multiple–Emitter Study.
6.9 Summary and Closing Comments.
Problems.
References.
Chapter 7. Gallium Arsenide and ESD.
7.1 Gallium Arsenide Technology and ESD.
7.2 Gallium Arsenide Energy–to–Failure and Power–to–Failure.
7.3 Gallium Arsenide ESD Failures in Active and Passive Elements.
7.4 Gallium Arsenide HBT Devices and ESD.
7.5 Gallium Arsenide HBT–Based Passive Elements.
7.6 Gallium Arsenide Technology Table of Failure Mechanisms.
7.7 Indium Gallium Arsenide and ESD.
7.8 Indium Phosphide (InP) and ESD.
7.9 Summary and Closing Comments.
Problems.
References.
Chapter 8. Bipolar Receiver Circuits and Bipolar ESD Networks.
8.1 Bipolar Receivers and ESD.
8.2 Single Ended Common–Emitter Receiver Circuits.
8.3 Bipolar Differential Receiver Circuits.
8.4 Bipolar ESD Input Circuits.
8.5 Bipolar–based ESD Power Clamps.
8.6 Bipolar ESD Diode String and Triple–Well Power Clamps.
8.7 Summary and Closing Comments.
Problems.
References.
Chapter 9. RF and ESD Computer–Aided Design (CAD).
9.1 RF ESD Design Environment.
9.2 ESD Design with Hierarchical Parameterized Cells.
9.3 ESD Design of RF CMOS–Based Hierarchical Parameterized Cells.
9.4 RF BiCMOS ESD Hierarchical Parameterized Cell.
9.5 Advantages and Limitations of the ESD Design System.
9.6 Guard Ring P–Cell Methodology.
9.7 Summary and Closing Comments.
Problems.
References.
Chapter 10. Alternative ESD Concepts: On–Chip and Off–Chip.
10.1 Spark Gaps.
10.2 Field Emission Devices.
10.3 Off–chip Protection and Off–Chip Transient Suppression Devices.
10.4 Off–Chip Transient Voltage Suppression (TVS) Devices.
10.5 Off–Chip Polymer Voltage Suppression (PVS) Devices.
10.6 Package–Level Mechanical ESD Solutions.
10.7 RF Proximity Communications Chip–to–Chip ESD Design Practices.
10.8 Summary and Closing Comments.
Problems.
References.
Index.