The performance of the deep sub-micron technology CMOS integrated circuits is limited by the wired chip-to-chip and on-chip interconnects. This work proposes two technologies for widening up this bottleneck. For the on-chip buses we propose the introduction of spatial and temporal coding techniques, which provide substantial increase of the data rate at the price of a simple coding hardware. The chip-to-chip interconnects can be implemented using wireless data transmission. The area-efficient on-chip antenna integration and the achievable chip-to-chip channel capacities are presented.