VHDL for Logic Synthesis
Autor Andrew Rushtonen Limba Engleză Hardback – 25 apr 2011
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Specificații
ISBN-13: 9780470688472
ISBN-10: 0470688475
Pagini: 496
Ilustrații: Illustrations
Dimensiuni: 175 x 250 x 31 mm
Greutate: 1.01 kg
Ediția:3rd edition
Editura: Wiley
Locul publicării:Chichester, United Kingdom
ISBN-10: 0470688475
Pagini: 496
Ilustrații: Illustrations
Dimensiuni: 175 x 250 x 31 mm
Greutate: 1.01 kg
Ediția:3rd edition
Editura: Wiley
Locul publicării:Chichester, United Kingdom
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Public țintă
Professional hardware engineers using VHDL for logic synthesisTextul de pe ultima copertă
Making VHDL a simple and easy–to–use hardware description language Many engineers encountering VHDL (very high speed integrated circuits hardware description language) for the first time can feel overwhelmed by it. This book bridges the gap between the VHDL language and the hardware that results from logic synthesis with clear organisation, progressing from the basics of combinational logic, types, and operators; through special structures such as tristate buses, register banks and memories, to advanced themes such as developing your own packages, writing test benches and using the full range of synthesis types.
This third edition has been substantially rewritten to include the new VHDL–2008 features that enable synthesis of fixed–point and floating–point hardware. Extensively updated throughout to reflect modern logic synthesis usage, it also contains a complete case study to demonstrate the updated features.
New to this edition:
This third edition has been substantially rewritten to include the new VHDL–2008 features that enable synthesis of fixed–point and floating–point hardware. Extensively updated throughout to reflect modern logic synthesis usage, it also contains a complete case study to demonstrate the updated features.
New to this edition:
- a common VHDL subset which will work across a range of different synthesis systems, targeting a very wide range of technologies
- a design style that results in long design lifetimes, maximum design reuse and easy technology retargeting
- a new chapter on a large scale design example based on a digital filter from design objective and design process, to testing strategy and test benches
- a chapter on writing test benches, with everything needed to implement a test–based design strategy
- extensive coverage of data path design, including integer, fixed–point and floating–point arithmetic, logic circuits, shifters, tristate buses, RAMs, ROMs, state machines, and decoders
Cuprins
Preface xi
List of Figures xv
List of Tables xvii
1 Introduction 1
1.1 The VHDL Design Cycle 1
1.2 The Origins of VHDL 2
1.3 The Standardisation Process 3
1.4 Unification of VHDL Standards 4
1.5 Portability 4
2 Register–Transfer Level Design 7
2.1 The RTL Design Stages 8
2.2 Example Circuit 8
2.3 Identify the Data Operations 10
2.4 Determine the Data Precision 12
2.5 Choose Resources to Provide 12
2.6 Allocate Operations to Resources 13
2.7 Design the Controller 14
2.8 Design the Reset Mechanism 15
2.9 VHDL Description of the RTL Design 15
2.10 Synthesis Results 16
3 Combinational Logic 19
3.1 Design Units 19
3.2 Entities and Architectures 20
3.3 Simulation Model 22
3.4 Synthesis Templates 25
3.5 Signals and Ports 27
3.6 Initial Values 29
3.7 Simple Signal Assignments 30
3.8 Conditional Signal Assignments 31
3.9 Selected Signal Assignment 33
3.10 Worked Example 34
4 Basic Types 37
4.1 Synthesisable Types 37
4.2 Standard Types 37
4.3 Standard Operators 38
4.4 Type Bit 39
4.5 Type Boolean 39
4.6 Integer Types 41
4.7 Enumeration Types 46
4.8 Multi–Valued Logic Types 47
4.9 Records 48
4.10 Arrays 49
4.11 Aggregates, Strings and Bit–Strings 53
4.12 Attributes 56
4.13 More on Selected Signal Assignments 60
5 Operators 63
5.1 The Standard Operators 63
5.2 Operator Precedence 64
5.3 Boolean Operators 70
5.4 Comparison Operators 73
5.5 Shifting Operators 76
5.6 Arithmetic Operators 79
5.7 Concatenation Operator 84
6 Synthesis Types 85
6.1 Synthesis Type System 85
6.2 Making the Packages Visible 87
6.3 Logic Types Std—Logic—1164 90
6.4 Numeric Types Numeric—Std 95
6.5 Fixed–Point Types Fixed—Pkg 105
6.6 Floating–Point Types Float—Pkg 119
6.7 Type Conversions 134
6.8 Constant Values 144
6.9 Mixing Types in Expressions 146
6.10 Top–Level Interface 147
7 Std—Logic—Arith 151
7.1 The Std—Logic—Arith Package 151
7.2 Contents of Std—Logic—Arith 152
7.3 Type Conversions 161
7.4 Constant Values 162
7.5 Mixing Types in Expressions 164
8 Sequential VHDL 167
8.1 Processes 167
8.2 Signal Assignments 170
8.3 Variables 171
8.4 If Statements 172
8.5 Case Statements 177
8.6 Latch Inference 178
8.7 Loops 181
8.8 Worked Example 187
9 Registers 191
9.1 Basic D–Type Register 191
9.2 Simulation Model 192
9.3 Synthesis Model 193
9.4 Register Templates 195
9.5 Register Types 199
9.6 Clock Types 199
9.7 Clock Gating 200
9.8 Data Gating 201
9.9 Asynchronous Reset 203
9.10 Synchronous Reset 208
9.11 Registered Variables 210
9.12 Initial Values 211
10 Hierarchy 213
10.1 The Role of Components 213
10.2 Indirect Binding 214
10.3 Direct Binding 219
10.4 Component Packages 220
10.5 Parameterised Components 222
10.6 Generate Statements 225
10.7 Worked Examples 230
11 Subprograms 243
11.1 The Role of Subprograms 243
11.2 Functions 243
11.3 Operators 254
11.4 Type Conversions 258
11.5 Procedures 261
11.6 Declaring Subprograms 267
11.7 Worked Example 270
12 Special Structures 279
12.1 Tristates 279
12.2 Finite State Machines 284
12.3 RAMs and Register Banks 292
12.4 Decoders and ROMs 297
13 Test Benches 301
13.1 Test Benches 301
13.2 Combinational Test Bench 302
13.3 Verifying Responses 305
13.4 Clocks and Resets 307
13.5 Other Standard Types 310
13.6 Don t Care Outputs 312
13.7 Printing Response Values 314
13.8 Using TextIO to Read Data Files 315
13.9 Reading Standard Types 318
13.10 TextIO Error Handling 319
13.11 TextIO for Synthesis Types 321
13.12 TextIO for User–Defined Types 322
13.13 Worked Example 325
14 Libraries 327
14.1 The Library 327
14.2 Library Names 328
14.3 Library Work 329
14.4 Standard Libraries 330
14.5 Organising Your Files 333
14.6 Incremental Compilation 335
15 Case Study 337
15.1 Specification 337
15.2 System–Level Design 338
15.3 RTL Design 340
15.4 Trial Synthesis 352
15.5 Testing the Design 353
15.6 Floating–Point Version 361
15.7 Final Synthesis 362
15.8 Generic Version 364
15.9 Conclusions 366
Appendix A Package Listings 369
A.1 Package Standard 369
A.2 Package Standard—Additions 373
A.3 Package Std—Logic—1164 380
A.4 Package Std—Logic—1164—Additions 383
A.5 Package Numeric—Std 389
A.6 Package Numeric—Std—Additions 393
A.7 Package Fixed—Float—Types 400
A.8 Package Fixed—Pkg 401
A.9 Package Float—Pkg 415
A.10 Package TextIO 429
A.11 Package Standard—Textio—Additions 431
A.12 Package Std—Logic—Arith 432
A.13 Package Math—Real 436
Appendix B Syntax Reference 439
B.1 Keywords 439
B.2 Design Units 440
B.3 Concurrent Statements 441
B.4 Sequential Statements 443
B.5 Expressions 444
B.6 Declarations 445
References 449
Index 451
List of Figures xv
List of Tables xvii
1 Introduction 1
1.1 The VHDL Design Cycle 1
1.2 The Origins of VHDL 2
1.3 The Standardisation Process 3
1.4 Unification of VHDL Standards 4
1.5 Portability 4
2 Register–Transfer Level Design 7
2.1 The RTL Design Stages 8
2.2 Example Circuit 8
2.3 Identify the Data Operations 10
2.4 Determine the Data Precision 12
2.5 Choose Resources to Provide 12
2.6 Allocate Operations to Resources 13
2.7 Design the Controller 14
2.8 Design the Reset Mechanism 15
2.9 VHDL Description of the RTL Design 15
2.10 Synthesis Results 16
3 Combinational Logic 19
3.1 Design Units 19
3.2 Entities and Architectures 20
3.3 Simulation Model 22
3.4 Synthesis Templates 25
3.5 Signals and Ports 27
3.6 Initial Values 29
3.7 Simple Signal Assignments 30
3.8 Conditional Signal Assignments 31
3.9 Selected Signal Assignment 33
3.10 Worked Example 34
4 Basic Types 37
4.1 Synthesisable Types 37
4.2 Standard Types 37
4.3 Standard Operators 38
4.4 Type Bit 39
4.5 Type Boolean 39
4.6 Integer Types 41
4.7 Enumeration Types 46
4.8 Multi–Valued Logic Types 47
4.9 Records 48
4.10 Arrays 49
4.11 Aggregates, Strings and Bit–Strings 53
4.12 Attributes 56
4.13 More on Selected Signal Assignments 60
5 Operators 63
5.1 The Standard Operators 63
5.2 Operator Precedence 64
5.3 Boolean Operators 70
5.4 Comparison Operators 73
5.5 Shifting Operators 76
5.6 Arithmetic Operators 79
5.7 Concatenation Operator 84
6 Synthesis Types 85
6.1 Synthesis Type System 85
6.2 Making the Packages Visible 87
6.3 Logic Types Std—Logic—1164 90
6.4 Numeric Types Numeric—Std 95
6.5 Fixed–Point Types Fixed—Pkg 105
6.6 Floating–Point Types Float—Pkg 119
6.7 Type Conversions 134
6.8 Constant Values 144
6.9 Mixing Types in Expressions 146
6.10 Top–Level Interface 147
7 Std—Logic—Arith 151
7.1 The Std—Logic—Arith Package 151
7.2 Contents of Std—Logic—Arith 152
7.3 Type Conversions 161
7.4 Constant Values 162
7.5 Mixing Types in Expressions 164
8 Sequential VHDL 167
8.1 Processes 167
8.2 Signal Assignments 170
8.3 Variables 171
8.4 If Statements 172
8.5 Case Statements 177
8.6 Latch Inference 178
8.7 Loops 181
8.8 Worked Example 187
9 Registers 191
9.1 Basic D–Type Register 191
9.2 Simulation Model 192
9.3 Synthesis Model 193
9.4 Register Templates 195
9.5 Register Types 199
9.6 Clock Types 199
9.7 Clock Gating 200
9.8 Data Gating 201
9.9 Asynchronous Reset 203
9.10 Synchronous Reset 208
9.11 Registered Variables 210
9.12 Initial Values 211
10 Hierarchy 213
10.1 The Role of Components 213
10.2 Indirect Binding 214
10.3 Direct Binding 219
10.4 Component Packages 220
10.5 Parameterised Components 222
10.6 Generate Statements 225
10.7 Worked Examples 230
11 Subprograms 243
11.1 The Role of Subprograms 243
11.2 Functions 243
11.3 Operators 254
11.4 Type Conversions 258
11.5 Procedures 261
11.6 Declaring Subprograms 267
11.7 Worked Example 270
12 Special Structures 279
12.1 Tristates 279
12.2 Finite State Machines 284
12.3 RAMs and Register Banks 292
12.4 Decoders and ROMs 297
13 Test Benches 301
13.1 Test Benches 301
13.2 Combinational Test Bench 302
13.3 Verifying Responses 305
13.4 Clocks and Resets 307
13.5 Other Standard Types 310
13.6 Don t Care Outputs 312
13.7 Printing Response Values 314
13.8 Using TextIO to Read Data Files 315
13.9 Reading Standard Types 318
13.10 TextIO Error Handling 319
13.11 TextIO for Synthesis Types 321
13.12 TextIO for User–Defined Types 322
13.13 Worked Example 325
14 Libraries 327
14.1 The Library 327
14.2 Library Names 328
14.3 Library Work 329
14.4 Standard Libraries 330
14.5 Organising Your Files 333
14.6 Incremental Compilation 335
15 Case Study 337
15.1 Specification 337
15.2 System–Level Design 338
15.3 RTL Design 340
15.4 Trial Synthesis 352
15.5 Testing the Design 353
15.6 Floating–Point Version 361
15.7 Final Synthesis 362
15.8 Generic Version 364
15.9 Conclusions 366
Appendix A Package Listings 369
A.1 Package Standard 369
A.2 Package Standard—Additions 373
A.3 Package Std—Logic—1164 380
A.4 Package Std—Logic—1164—Additions 383
A.5 Package Numeric—Std 389
A.6 Package Numeric—Std—Additions 393
A.7 Package Fixed—Float—Types 400
A.8 Package Fixed—Pkg 401
A.9 Package Float—Pkg 415
A.10 Package TextIO 429
A.11 Package Standard—Textio—Additions 431
A.12 Package Std—Logic—Arith 432
A.13 Package Math—Real 436
Appendix B Syntax Reference 439
B.1 Keywords 439
B.2 Design Units 440
B.3 Concurrent Statements 441
B.4 Sequential Statements 443
B.5 Expressions 444
B.6 Declarations 445
References 449
Index 451