Constraining Designs for Synthesis and Timing Analysis: A Practical Guide to Synopsys Design Constraints (SDC)
Autor Sridhar Gangadharan et al.
23 iun 2015
Paperback
Preț: 662.65 lei 779.59 lei
6-8 săpt.
-15%
Cărți de Sanjay Churiwala
Principles of VLSI RTL Design
Autor Sanjay Churiwala et al.
12 mai 2011
Hardback
Preț: 751.33 lei 916.25 lei
6-8 săpt.
-18%
Designing with Xilinx® FPGAs: Using Vivado
Editat de Sanjay Churiwala
7 iul 2018
Paperback
Preț: 614.60 lei 723.05 lei
6-8 săpt.
-15%
An Introduction to Machine Learning
Autor Gopinath Rebala et al.
17 mai 2019
Hardback
Preț: 861.00 lei 1050.00 lei
6-8 săpt.
-18%