Integrated Fiber-Optic Receivers
Autor Aaron Buchwald, Kenneth W. Martinen Limba Engleză Paperback – 27 sep 2012
Because theoretical concepts are generally grasped more easily by example, Part II is devoted to circuit design issues that illustrate example realizations of architectures described in Part I. Part II presents the transistor-level design, and measured results, of fundamental building blocks and test circuits.
For practicing engineers, more than just reporting on the results of specific circuits, this book serves as a tutorial on the design of integrated high-speed broadband PAM data systems, such as: repeaters in long-haul, fiber-optic, trunk-lines transceivers for use in LANs and WANs; read channels for high-density data storage devices; and wireless communication handsets. Integrated Fiber-Optic Receivers may be used as a text for advanced courses in both analog circuit design and communication systems.
| Toate formatele și edițiile | Preț | Express |
|---|---|---|
| Paperback (1) | 1180.00 lei 43-57 zile | |
| Springer – 27 sep 2012 | 1180.00 lei 43-57 zile | |
| Hardback (1) | 1182.47 lei 43-57 zile | |
| Springer Us – 31 mai 1995 | 1182.47 lei 43-57 zile |
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Specificații
ISBN-13: 9781461359449
ISBN-10: 1461359449
Pagini: 488
Ilustrații: XXI, 462 p.
Dimensiuni: 155 x 235 x 27 mm
Greutate: 0.73 kg
Ediția:Softcover reprint of the original 1st ed. 1995
Editura: Springer
Locul publicării:New York, NY, United States
ISBN-10: 1461359449
Pagini: 488
Ilustrații: XXI, 462 p.
Dimensiuni: 155 x 235 x 27 mm
Greutate: 0.73 kg
Ediția:Softcover reprint of the original 1st ed. 1995
Editura: Springer
Locul publicării:New York, NY, United States
Public țintă
ResearchCuprins
I System Considerations.- 1 Integrated Fiber-Optic Receivers.- 2 Mathematical Preliminaries.- 3 Optimal Decision Theory.- 4 Clock Recovery.- 5 Practical High-Speed Clock Recovery.- II Circuit Design.- 6 Heterojunction Bipolar Transistors.- 7 Low-Noise Preamplifier.- 8 Voltage Controlled Oscillators.- 9 6-GHz Phase-Lock Loop.- 10 Clock Recovery and Data Retiming IC.