Name: Hierarchical Annotated Action Diagrams
Price: 662.95 RON
Availability: OnlineOnly
Author: Eduard Cerny
ISBN: 9780792383017

Hierarchical Annotated Action Diagrams

Eduard Cerny

Karim Khordoc

Pierre Girodias

Bachir Berkane

Standardization of hardware description languages and the availability of synthesis tools has brought about a remarkable increase in the productivity of hardware designers. Yet design verification methods and tools lag behind and have difficulty in dealing with the increasing design complexity. This may get worse because more complex systems are now constructed by (re)using Intellectual Property blocks developed by third parties. To verify such designs, abstract models of the blocks and the system must be developed, with separate concerns, such as interface communication, functionality, and timing, that can be verified in an almost independent fashion. Standard Hardware Description Languages such as VHDL and Verilog are inspired by procedural `imperative' programming languages in which function and timing are inherently intertwined in the statements of the language. Furthermore, they are not conceived to state the intent of the design in a simple declarative way that contains provisions for design choices, for stating assumptions on the environment, and for indicating uncertainty in system timing.
Hierarchical Annotated Action Diagrams: An Interface-Oriented Specification and Verification Method presents a description methodology that was inspired by Timing Diagrams and Process Algebras, the so-called Hierarchical Annotated Diagrams. It is suitable for specifying systems with complex interface behaviors that govern the global system behavior. A HADD specification can be converted into a behavioral real-time model in VHDL and used to verify the surrounding logic, such as interface transducers. Also, function can be conservatively abstracted away and the interactions between interconnected devices can be verified using Constraint Logic Programming based on Relational Interval Arithmetic.
Hierarchical Annotated Action Diagrams: An Interface-Oriented Specification and Verification Method is ofinterest to readers who are involved in defining methods and tools for system-level design specification and verification. The techniques for interface compatibility verification can be used by practicing designers, without any more sophisticated tool than a calculator.

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Cuprins

1 Introduction.- 1.1 Digital System Design and Verification.- 1.2 Interface-Oriented Models.- 1.3 Purpose and Organization of the Book.- 2 Overview of HAAD Method.- 2.1 Leaf Action Diagrams.- 2.2 Annotations in Leaf Action Diagrams.- 2.3 Hierarchical Action Diagrams.- 2.4 Annotations in HAAD Hierarchy.- 3 Formal Characterization of HAAD.- 3.1 Leaf-Level Action Diagram Algebra.- 3.2 Verification.- 3.3 Language of Hierarchical Action Diagrams.- 3.4 Related work.- 4 HAAD VHDL Model.- 4.1 Execution of HAAD VHDL Models.- 4.2 Execution of Hierarchical Action Diagrams.- 4.3 Occurrence Time Enumeration of Output Actions.- 4.4 Enumeration and Delay Correlation.- 4.5 Organization of a HAAD Model in VHDL.- 5 Consistency, Causality and Compatibility.- 5.1 Introduction.- 5.2 Basic Concepts.- 5.3 Problems.- 5.4 BlockMachines.- 5.5 Derived Block Machines.- 5.6 Causal Action Diagrams.- 5.7 Compatibility of Action Diagrams.- 5.8 Conclusions.- 6 Interface Verification using CLP.- 6.1 Interface Timing Verification.- 6.2 Constraint Logic Programming.- 6.3 The Event Separation Problem.- 6.4 Delay Correlation.- 6.5 CSP and CLP Based on RIA.- 6.6 Solving ITV with CLP Based on RIA.- 6.7 Examples.- 6.8 Experimental Results.- 6.9 Concluding Remarks.- 7 Example: Interfacing ARM7 and a Static RAM.- 7.1 Problem Definition.- 7.2 Bus Functional Model of ARM7 Subset.- 7.3 Bus Functional Model of RAM.- 7.4 VHDL Model of interface transducer.- 7.5 Putting it all together.- 7.6 Static Interface Timing Verification.- 8 Summary and Recent Developments.- 8.1 Summary.- 8.2 Recent Developments.- 8.3 Future Directions.- References.- A Grammar of the HAAD Language.- A.1 Conventions.- A.2 Semantic Notes.- A.2.1 Generics.- A.2.2 Name Spaces.- A.2.3 Default Constraint Bounds.- A.3 Grammar Definition.- B Proofs forChapter.- B.1 Proof of Theorem 3.1.- B.2 Proof of Theorem 3.2, 3.3, 3.4, and 3.5.- B.3 Proof of Theorem 3.6.- B.4 Proof of Theorem 3.7.- B.5 Proof of Theorem 8.- B.6 Proof of Theorem 3.9.- B.7 Proof of Theorem 3.10.

Notă biografică

Janick Bergeron is a Scientist at Synopsys, Inc. He is the author of the best-selling book Writing Testbenches: Functional Verification of HDL Models and the moderator of the Verification Guild. Prior to joining Synopsys, Janick worked on verification methodology at Qualis Design Corporation and Bell-Northern Research. He holds a Masters degree in Electrical Engineering from the University of Waterloo, a Bachelor of Science degree in Engineering from the Université du Québec, and an MBA degree granted through the University of Oregon. Eduard Cerny is a Principal Engineer, R&D, in the Verification Group at Synopsys, Inc. He joined Synopsys in 2001 after 25 years in academia, as Professor of Computer Science at the Université de Montréal. Eduard has a B.Sc. in Electrical Engineering from Loyola College in Montreal, Canada, and a M.Eng. and Ph.D. in Electrical Engineering from McGill University in Montreal, Canada. His interests have been in design, verification and test of hardware, and he is author of many articles in these areas. Alan Hunter, BEng(Hons), MSc, is the Design Verification Methodology Programme manager at ARM Ltd. and is leading the design verification methodology work for ARM worldwide. This work covers all areas from CPU design verification through systems and system component design verification. His main areas of interest include optimizing design verification efficiency and quality, formal methods, and determinism in the design verification flow. Prior to joining ARM, Alan worked for a small formal verification company specializing in property and equivalence checking. Andy Nightingale, BEng(Hons), MBCS CITP, is a consultant engineer at ARM Ltd and has led the SoC Verification group in ARM's Cambridge and Sheffield design centers for the past four years. The group covers ARM PrimeXSys platforms and PrimeCell development, including advanced AXI- and AHB-based system backplanecomponents such as bus interconnects and high-performance memory controllers. Prior to working at ARM, Andy worked as a real-time embedded systems engineer for a successful scientific instrument company, primarily serving the semiconductor industry.