Formal Methods in Computer-Aided Design
Editat de Mark D. Aagaard, John W. O'Learyen Limba Engleză Paperback – 23 oct 2002
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Specificații
ISBN-13: 9783540001164
ISBN-10: 3540001166
Pagini: 420
Ilustrații: XII, 408 p.
Dimensiuni: 155 x 235 x 23 mm
Greutate: 0.63 kg
Ediția:2002
Editura: Springer
Locul publicării:Berlin, Heidelberg, Germany
ISBN-10: 3540001166
Pagini: 420
Ilustrații: XII, 408 p.
Dimensiuni: 155 x 235 x 23 mm
Greutate: 0.63 kg
Ediția:2002
Editura: Springer
Locul publicării:Berlin, Heidelberg, Germany
Public țintă
ResearchCuprins
Abstraction.- Abstraction by Symbolic Indexing Transformations.- Counter-Example Based Predicate Discovery in Predicate Abstraction.- Automated Abstraction Refinement for Model Checking Large State Spaces Using SAT Based Conflict Analysis.- Symbolic Simulation.- Simplifying Circuits for Formal Verification Using Parametric Representation.- Generalized Symbolic Trajectory Evaluation — Abstraction in Action.- Model Checking: Strongly-Connected Components.- Analysis of Symbolic SCC Hull Algorithms.- Sharp Disjunctive Decomposition for Language Emptiness Checking.- Microprocessor Specification and Verification.- Relating Multi-step and Single-Step Microprocessor Correctness Statements.- Modeling and Verification of Out-of-Order Microprocessors in UCLID.- Decision Procedures.- On Solving Presburger and Linear Arithmetic with SAT.- Deciding Presburger Arithmetic by Model Checking and Comparisons with Other Methods.- Qubos: Deciding Quantified Boolean Logic Using Propositional Satisfiability Solvers.- Model Checking: Reachability Analysis.- Exploiting Transition Locality in the Disk Based Mur? Verifier.- Traversal Techniques for Concurrent Systems.- Model Checking: Fixed Points.- A Fixpoint Based Encoding for Bounded Model Checking.- Using Edge-Valued Decision Diagrams for Symbolic Generation of Shortest Paths.- Verification Techniques and Methodology.- Mechanical Verification of a Square Root Algorithm Using Taylor’s Theorem.- A Specification and Verification Framework for Developing Weak Shared Memory Consistency Protocols.- Model Checking the Design of an Unrestricted, Stuck-at Fault Tolerant, Asynchronous Sequential Circuit Using SMV.- Hardware Description Languages.- Functional Design Using Behavioural and Structural Components.- Compiling Hardware Descriptions withRelative Placement Information for Parametrised Libraries.- Prototyping and Synthesis.- Input/Output Compatibility of Reactive Systems.- Smart Play-out of Behavioral Requirements.