The goal of this research work is to implement a digital integrator having large bandwidth and high accuracy. we optimized the digital implementation of integrator on virtex5 (xc5vlx110t -1). The operating range of a digital wideband integrator is from 0 to π rad/sample. For accurate integration of random signal, a large analog bandwidth (in unit of rad/second) integrator is needed. In order to optimize analog bandwidth, structure of the digital integrator as well as architecture of involved arithmetic logic is studied. Our design is then compared to DSP-48 slices (hard macros) based design on FPGA as well as system generator(auto programming feature) based design on the same FPGA. Our RTL design achieved higher bandwidth of 40.970MHz compared with other two designs of 30.234 MHz and 29.016 MHz respectively. The integrator can integrate zero mean value signal only, so for verification of the design on FPGA, a pair of ADC and DAC is interfaced with the FPGA. On FPGA we implemented a digital High pass filter (to remove dc component and obtaining zero mean value signal) and proposed an integrator. Behavior of the integrator was then characterized using CRO, visually.