For many years, the dominant fault model in automatic test pattern gen­ eration (ATPG) for digital integrated circuits has been the stuck-at fault model. The static nature of stuck-at fault testing when compared to the extremely dynamic nature of integrated circuit (IC) technology has caused many to question whether or not stuck-at fault based testing is still viable. Attempts at answering this question have not been wholly satisfying due to a lack of true quantification, statistical significance, and/or high computational expense. In this monograph we introduce a methodology to address the ques­ tion in a manner which circumvents the drawbacks of previous approaches. The method is based on symbolic Boolean functional analyses using Or­ dered Binary Decision Diagrams (OBDDs). OBDDs have been conjectured to be an attractive representation form for Boolean functions, although cases ex­ ist for which their complexity is guaranteed to grow exponentially with input cardinality. Classes of Boolean functions which exploit the efficiencies inherent in OBDDs to a very great extent are examined in Chapter 7. Exact equa­ tions giving their OBDD sizes are derived, whereas until very recently only size bounds have been available. These size equations suggest that straight­ forward applications of OBDDs to design and test related problems may not prove as fruitful as was once thought.