3D Integration for NoC-based SoC Architectures: Integrated Circuits and Systems
Editat de Abbas Sheibanyrad, Frédéric Pétrot, Axel Jantschen Limba Engleză Hardback – 10 dec 2010
| Toate formatele și edițiile | Preț | Express |
|---|---|---|
| Paperback (1) | 669.59 lei 6-8 săpt. | |
| Springer – 27 dec 2012 | 669.59 lei 6-8 săpt. | |
| Hardback (1) | 913.32 lei 6-8 săpt. | |
| Springer – 10 dec 2010 | 913.32 lei 6-8 săpt. |
Din seria Integrated Circuits and Systems
- 15%
Preț: 632.81 lei - 15%
Preț: 624.77 lei - 15%
Preț: 609.53 lei - 24%
Preț: 869.94 lei - 20%
Preț: 958.63 lei - 18%
Preț: 912.40 lei - 20%
Preț: 618.78 lei - 18%
Preț: 1334.56 lei - 23%
Preț: 989.82 lei - 15%
Preț: 610.82 lei - 15%
Preț: 668.34 lei - 18%
Preț: 917.40 lei - 18%
Preț: 851.28 lei - 15%
Preț: 616.95 lei - 18%
Preț: 913.32 lei - 20%
Preț: 949.76 lei - 18%
Preț: 1166.27 lei - 18%
Preț: 1179.60 lei - 23%
Preț: 617.56 lei - 15%
Preț: 610.82 lei - 18%
Preț: 915.89 lei - 18%
Preț: 916.19 lei - 18%
Preț: 915.13 lei - 24%
Preț: 871.66 lei - 18%
Preț: 962.43 lei - 15%
Preț: 625.75 lei - 18%
Preț: 910.11 lei - 18%
Preț: 916.80 lei - 15%
Preț: 609.71 lei - 18%
Preț: 913.62 lei - 18%
Preț: 908.00 lei - 18%
Preț: 904.53 lei - 15%
Preț: 672.43 lei - 18%
Preț: 906.17 lei - 15%
Preț: 669.59 lei - 18%
Preț: 850.82 lei - 18%
Preț: 904.53 lei - 18%
Preț: 1017.33 lei - 15%
Preț: 616.64 lei
Preț: 913.32 lei
Preț vechi: 1113.81 lei
-18% Nou
Puncte Express: 1370
Preț estimativ în valută:
161.62€ • 189.51$ • 141.93£
161.62€ • 189.51$ • 141.93£
Carte tipărită la comandă
Livrare economică 10-24 februarie 26
Preluare comenzi: 021 569.72.76
Specificații
ISBN-13: 9781441976178
ISBN-10: 1441976175
Pagini: 290
Ilustrații: X, 278 p.
Dimensiuni: 152 x 229 x 28 mm
Greutate: 0.58 kg
Ediția:2011
Editura: Springer
Colecția Springer
Seria Integrated Circuits and Systems
Locul publicării:New York, NY, United States
ISBN-10: 1441976175
Pagini: 290
Ilustrații: X, 278 p.
Dimensiuni: 152 x 229 x 28 mm
Greutate: 0.58 kg
Ediția:2011
Editura: Springer
Colecția Springer
Seria Integrated Circuits and Systems
Locul publicării:New York, NY, United States
Public țintă
Professional/practitionerCuprins
Three-Dimensional Integration of Integrated Circuits - an Introduction.- The Promises and Limitation of 3-D Integration.- Testing 3D Stacked ICs Containing Through-Silicon Vias.- Design and Computer Aided Design of 3DIC.- Physical Analysis of NoC Topologies for 3-D Integrated Systems.- Three-Dimensional Networks-on-Chip: Performance Evaluation.- Asynchronous 3D-NoCs.- Design of Application-Specific 3D Networks-on-Chip Architectures.- 3D Network on Chip Topology Synthesis: Designing Custom Topologies for Chip Stacks.- 3-D NoC on Inductive Wireless Interconnect.- Influence of Stacked 3D Memory/Cache architectures on GPUs.
Textul de pe ultima copertă
Back Cover CopySERIES:Integrated Circuits and Systems 3D-Integration for NoC-based SoC Architectures by: (Editors)Abbas Sheibanyrad Frédéric Petrot Axel Janstch This book investigates on the promises, challenges, and solutions for the 3D Integration (vertically stacking) of embedded systems connected via a network on a chip. It covers the entire architectural design approach for 3D-SoCs. 3D-Integration technologies, 3D-Design techniques, and 3D-Architectures have emerged as topics critical for current R&D leading to a broad range of products. This book presents a comprehensive, system-level overview of three-dimensional architectures and micro-architectures. •Presents a comprehensive, system-level overview of three-dimensional architectures and micro-architectures; •Covers the entire architectural design approach for 3D-SoCs;•Includes state-of-the-art treatment of 3D-Integration technologies, 3D-Design techniques, and 3D-Architectures.
Caracteristici
Provides a detailed background on the state of error control methods for on-chip interconnects, including Error Control Coding, Double Sampling, and On-Line Testing Describes the use of more complex concatenated codes such as Hamming Product Codes with Type-II HARQ, while emphasizing integration techniques for on-chip interconnect links Presents techniques for managing intermittent and permanent errors using a non-interrupting in-line test method with spare wire replacement Includes supplementary material: sn.pub/extras