This book presents a VLSI design methodology utilizing a buffer-based data flow to reduce interconnect resources and to synchronize the data transfer between different processing elements. The buffer-based dataflow is a novel design representation suitable for implementing data-centric applications. Since the buffer-based dataflow isolates the functional execution and data transfer of each node by using parameterized buffer controllers, it is helpful for reducing overall design time and for increasing reconfigurability. By manipulating the buffer-based dataflow, this book develops the sharing methodology that reduces interconnect resources in a complex VLSI design. Also, the book introduces the mapping methodology that synthesizes a buffer-based dataflow onto a reconfigurable SOC platform.