VHDL 101: Everything you Need to Know to Get Started
Autor William Kafigen Limba Engleză Paperback – 27 ian 2011
Bill Kafig, industry expert, swiftly brings the reader up to speed on techniques and functions commonly used in VHDL (VHSIC Hardware Description Language) as well as commands and data types. Extensive simple, complete designs accompany the content for maximum comprehension. The book concludes with a section on design re-use, which is of utmost importance to today's engineer who needs to meet a deadline and lower costs per unit.
*Gets you up to speed with VHDL fast, reducing time to market and driving down costs
*Covers the basics including language concepts and includes complete design examples for ease of learning
* Covers widely accepted industry nomenclature
* Learn from "best design practices"
- Gets you up to speed with VHDL fast, reducing time to market and driving down costs
- Covers the basics including language concepts and includes complete design examples for ease of learning
- Covers widely accepted industry nomenclature
- Learn from "best design practices"
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Specificații
ISBN-13: 9781856177047
ISBN-10: 1856177041
Pagini: 200
Dimensiuni: 191 x 235 x 15 mm
Greutate: 0.39 kg
Editura: ELSEVIER SCIENCE
ISBN-10: 1856177041
Pagini: 200
Dimensiuni: 191 x 235 x 15 mm
Greutate: 0.39 kg
Editura: ELSEVIER SCIENCE
Public țintă
Electrical engineers, hardware engineers, and students that have no FPGA or VHDL experienceCuprins
Chapter
1:
Introduction
and
Background:
VHDL;
Brief
History
of
VHDL;
FPGA
Architecture
Chapter 2: Overview of the Process of Implementing an FPGA Design: Design Entry; Synthesis; Simulation; Implementation; Bitstream Generation
Chapter 3: Loop 1 - Going with the Flow: The Shape of VHDL
Chapter 4: Loop 2 - Going Deeper: Introducing Processes, Variables and Sequential Statements: Tool Perspectives - Synthesis Options and Constraints
Chapter 5: Loop 3: Introducing Concept of Reuse; Flexibility Using Generics and Constants; Functions and Procedures; Attributes; Packages; Commonly Used Libraries
Appendix
A.1 Language Constructs
A.2 Data Types
A.3 Standard Libraries
Index
Chapter 2: Overview of the Process of Implementing an FPGA Design: Design Entry; Synthesis; Simulation; Implementation; Bitstream Generation
Chapter 3: Loop 1 - Going with the Flow: The Shape of VHDL
Chapter 4: Loop 2 - Going Deeper: Introducing Processes, Variables and Sequential Statements: Tool Perspectives - Synthesis Options and Constraints
Chapter 5: Loop 3: Introducing Concept of Reuse; Flexibility Using Generics and Constants; Functions and Procedures; Attributes; Packages; Commonly Used Libraries
Appendix
A.1 Language Constructs
A.2 Data Types
A.3 Standard Libraries
Index