Cantitate/Preț
Produs
Total produse
Vezi coșul
Switching Theory for Logic Synthesis de Tsutomu Sasao

Switching Theory for Logic Synthesis

Autor Tsutomu Sasao
en Limba Engleză Hardback – 28 feb 1999
Switching Theory for Logic Synthesis covers the basic topics of switching theory and logic synthesis in fourteen chapters. Chapters 1 through 5 provide the mathematical foundation. Chapters 6 through 8 include an introduction to sequential circuits, optimization of sequential machines and asynchronous sequential circuits. Chapters 9 through 14 are the main feature of the book. These chapters introduce and explain various topics that make up the subject of logic synthesis: multi-valued input two-valued output function, logic design for PLDs/FPGAs, EXOR-based design, and complexity theories of logic networks.
An appendix providing a history of switching theory is included. The reference list consists of over four hundred entries.
Switching Theory for Logic Synthesis is based on the author's lectures at Kyushu Institute of Technology as well as seminars for CAD engineers from various Japanese technology companies.
Switching Theory for Logic Synthesis will be of interest to CAD professionals and students at the advanced level. It is also useful as a textbook, as each chapter contains examples, illustrations, and exercises.
Citește tot Restrânge

Preț: 102853 lei

Preț vechi: 128566 lei
-20%

Puncte Express: 1543
Paperback 95276 lei
Hardback 102853 lei

Carte tipărită la comandă

Livrare economică 20 noiembrie-04 decembrie

Livrare prin curier în România Termenul estimat este afișat lângă disponibilitate.
Transport gratuit pentru acest produs Plată online sau ramburs, în funcție de opțiunile comenzii.
Retur gratuit în 14 zile Comandă securizată și suport în română.
 Adaugă în coș

Wish list
Gift list
Am citit!
Adaugă în listă

Specificații

ISBN-13: 9780792384564
ISBN-10: 0792384563
Pagini: 380
Ilustrații: XI, 362 p.
Dimensiuni: 160 x 241 x 25 mm
Greutate: 0.68 kg
Ediția:1999
Editura: Springer Us
Locul publicării:New York, NY, United States

Public țintă

Research

Cuprins

1 Mathematical Foundation.- 1.1 Set.- 1.2 Relation.- 1.3 Equivalence Class.- 1.4 Function.- 1.5 Ordered Set.- 2 Lattice and Boolean Algebra.- 2.1 Algebra.- 2.2 Lattice.- 2.3 Distributive Lattice and Complemented Lattice.- 2.4 Boolean Algebra.- 2.5 Logic Function.- 2.6 Group, Ring, and Field.- 3 Logic Functions and Their Representations.- 3.1 Logic Elements and Logic Networks.- 3.2 Logic Functions and Combinational Networks.- 3.3 SOP and POS.- 3.4 Shannon Expansion.- 3.5 Reed-Muller Expression.- 3.6 Logical Expressions and Multi-Level Logic Networks.- 3.7 Binary Decision Diagram.- 3.8 Comparison of Representation Methods.- 3.9 Logical Equations and Propositional Calculus.- 4 Optimization of and-or Two-Level Logic Networks.- 4.1 SOPs and Two-Level Logic Networks.- 4.2 n-Dimensional Cube.- 4.3 Karnaugh Map.- 4.4 Prime Implicant.- 4.5 Minimum SOP.- 4.6 Simplification of SOPs with Karnaugh Map.- 4.7 Quine-McCluskey Method.- 4.8 MSOPs and their Applications.- 4.9 Simplification of Multi-Output Networks.- 5 Logic Functions with Various Properties.- 5.1 Self-Dual Function.- 5.2 Monotone Function and Unate function.- 5.3 Linear Function.- 5.4 Symmetric Function.- 5.5 Threshold Function.- 5.6 Universal Set of Logic Functions.- 5.7 Equivalence Classes of Logic Functions.- 6 Sequential Networks.- 6.1 Introduction to Sequential Networks.- 6.2 Flip-Flops.- 6.3 Representation of Sequential Networks.- 6.4 State Assignment and State Table.- 6.5 Realization of Sequential Networks.- 7 Optimization of Sequential Networks.- 7.1 Optimization of Completely Specified Sequential Machines.- 7.2 Optimization of Incompletely Specified Sequential Machines.- 7.3 State Assignment.- 8 Delay and Asynchronous Behavior.- 8.1 Transient Response of Combinational Networks.- 8.2 Asynchronous Sequential Networks.- 8.3 Malfunctions of Asynchronous Sequential Networks.- 9 Multi-Valued Input Two-Valued Output Function.- 9.1 Multi-Valued Input Two-Valued Output Function.- 9.2 Bit Representation.- 9.3 Restriction.- 9.4 Tautology.- 9.5 Inclusion Relation.- 9.6 Equivalence.- 9.7 Divide and Conquer Method.- 9.8 Complementation of SOPs.- 9.9 Tautology Decision.- 9.10 Generation of Prime Implicants.- 9.11 Sharp Operation.- 10 Heuristic Optimization of Two-Level Networks.- 10.1 Simplification of SOPs with Many Inputs.- 10.2 Merge, Expansion, and Delete.- 10.3 Reduce and Reshape.- 10.4 Detection of Essential Prime Implicants.- 10.5 Multi-Output Function.- 10.6 PRESTO.- 10.7 MINI and ESPRESSO.- 10.8 Encoding Method for Combinational Networks.- 10.9 State Assignment for Sequential Networks.- 11 Multi-Level Logic Synthesis.- 11.1 Logic Synthesis System.- 11.2 Factoring using Product Terms.- 11.3 Two-Variable Function Generator.- 11.4 Algebraic Division of Logical Expressions.- 11.5 Functional Decomposition.- 11.6 Transformation of Networks.- 11.7 Simplification using Don’t Care.- 11.8 Boolean Relation.- 11.9 Timing Optimization.- 12 Logic Design Using Modules.- 12.1 Logic Design using PLAs.- 12.2 Design using Multiplexers.- 12.3 Logic Design using ROMs.- 13 Logic Design Using Exors.- 13.1 Classification of AND-EXOR Expressions.- 13.2 Simplification of ESOPs.- 13.3 Fault Detection and Boolean Difference.- 14 Complexity of Logic Networks.- 14.1 Complexity of Two-Level Logic Networks.- 14.2 Complexity of Multi-Level Logic Networks.- A History of Switching Theory.- References.

Notă biografică

Tsutomu Sasao received the B.E., M.E., and Ph.D. degrees in Electronics Engineering from Osaka University, Osaka Japan, in 1972, 1974, and 1977, respectively. He has held faculty/research positions at Osaka University, Japan; IBM T. J. Watson Research Center, Yorktown Heights, NY; the Naval Postgraduate School, Monterey, CA; and Kyushu Institute of Technology, Iizuka, Japan. Now, he is a Professor at the Department of Computer Science, Meiji University, Kawasaki, Japan. His research areas include logic design and switching theory, representations of logic functions, and multiple-valued logic. He has published more than 9 books on logic design including, Logic Synthesis and Optimization, Representation of Discrete Functions, Switching Theory for Logic Synthesis, Logic Synthesis and Verification, and Memory-Based Logic Synthesis, in 1993, 1996, 1999, 2001, and 2011, respectively. He has served Program Chairman for the IEEE International Symposium on Multiple-Valued Logic (ISMVL) many times. Also, he was the Symposium Chairman of the 28th ISMVL held in Fukuoka, Japan, in 1998. He received the NIWA Memorial Award in 1979, Takeda Techno-Entrepreneurship Award in 2001, and Distinctive Contribution Awards from IEEE Computer Society MVL-TC for papers presented at ISMVLs in 1986, 1996, 2003, 2004, and 2013. He has served as an associate editor of the IEEE Transactions on Computers. He is a Fellow of the IEEE.
Jon T. Butler received the B.E.E. and M.Engr. degrees from Rensselaer Polytechnic Institute, Troy, New York, in 1966 and 1967, respectively. He received the Ph.D. degree from The Ohio State University, Columbus, Ohio, in 1973. From 1987 until 2010, he was a Professor at the Naval Postgraduate School, Monterey, California. From 1974 to 1987, he was at Northwestern University, Evanston, Illinois. He isnow a Distinguished Professor Emeritus. During that time he served two periods of leave at the Naval Postgraduate School, first as a National Research Council Senior Postdoctoral Associate (1980-1981) and second as the NAVALEX Chair Professor (1986-1987). He served one period of leave as a foreign visiting professor at the Kyushu Institute of Technology, Iizuka, Japan. His research interests include logic optimization, multiple-valued logic, and reconfigurable computing. He has served on the editorial boards of the IEEE Transactions on Computers, Computer, and the IEEE Computer Society Press. He has served as the editor-in-chief of Computer and the IEEE Computer Society Press. He received the Award of Excellence, the Outstanding Contributed Paper Award, and a Distinctive Contributed Paper Award for papers presented at the International Symposium on Multiple-Valued Logic. He received the Distinguished Service Award, two Meritorious Awards, and nine Certificates of Appreciation for service to the IEEE Computer Society. He is a Life Fellow of the IEEE.