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Power Integrity for Nanoscale Integrated Systems de Masanori Hashimoto

Power Integrity for Nanoscale Integrated Systems

Autor Masanori Hashimoto, Raj Nair
en Limba Engleză Hardback – 16 mar 2014

Publisher's Note: Products purchased from Third Party sellers are not guaranteed by the publisher for quality,  authenticity, or access to any online entitlements included with the product.

Proven methods for noise-tolerant nanoscale integrated circuit design
This leading-edge guide discusses the impact of power integrity from a design perspective, emphasizing phenomena and problems induced by power integrity degradation and the latest design trends, including low-power design. Power Integrity for Nanoscale Integrated Systems describes how these problems can be forecast early in the design process and the countermeasures that can be used to address them, such as the inclusion of inductance and accurate modeling for PI analysis, as well as robust circuit design. Detailed examples and a case study on the IBM POWER7+ processor illustrate real-world applications of the techniques presented in this practical resource.
Coverage includes:
  • Significance of power integrity for integrated circuits
  • Supply and substrate noise impact on circuits
  • Clock generation and distribution with power integrity
  • Signal and power integrity design for I/O circuits
  • Power integrity degradation and modeling
  • Lumped, distributed, and 3D modeling for power integrity
  • Chip temperature and PI impact
  • Low-power techniques and PI impact
  • Power integrity case study using the IBM POWER7+ processor chip
  • Carbon nanotube interconnects for power delivery
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Specificații

ISBN-13: 9780071787765
ISBN-10: 0071787763
Pagini: 416
Dimensiuni: 208 x 229 x 26 mm
Greutate: 0.7 kg
Editura: McGraw Hill Education
Colecția McGraw-Hill
Locul publicării:United States

Cuprins

Ch. 1: Significance of Power Integrity for Integrated Circuits
Ch. 2. Supply and Substrate Noise Impact on Circuits
Ch. 3. Clock Generation and Clock Distribution with PI Degradation
Ch. 4. Chip IO Circuits and PI
Ch. 5. Modeling of Circuits and IP Cores for PI Analysis
Ch. 6. Power Integrity Degradation and Modeling
Ch. 7. Lowe Power Techniques and PI Impact
Ch. 8. Chip Temperature and PI Impact
Ch. 9. Case Study: Chip ZZZZZ, Inferences and Conclusions
Ch. 10. PI in the Nanotechnology Realm

Notă biografică

Masanori Hashimoto is an Associate Professor in the department of Information Systems and Engineering, Graduate School of Information Science Technology, Osaka University. He has been working on modeling and measurement of on-chip power supply noise and signal coupling noise. Professor Hashimoto's research interests include timing, power, and signal integrity analysis, ultra-low power design, design for reliability, performance optimization in physical design, and on-chip high-speed signaling. He has co-authored several journal articles.

Raj Nair, a consultant in IC power delivery and power integrity, is co-founder of Anasim Corporation, which commercializes power integrity and energy aware SoC (System on Chip) design tools.