Instead of the costly RFID reader, WNIC can be used to communicate with the RFID transponder. However, the memory block, which is one of the major parts in RFID transponder, has to be redesigned. This book is concentrated on designing an improved CMOS Sense Amplifier (SA) and Charge Pump (CP) circuits, which are compatible for readerless RFID transponder EEPROM. Memory read access time; power dissipation and the reliability of an EEPROM are strongly influenced by the performance of the SA. Moreover, to reduce the continuous power supply in integrated circuits, CP circuit is widely used to direct charge flow and to generate boosted output voltage higher than VDD in EEPROM. The SA is designed to work in low voltage while the CP is designed for achieving low power, free from threshold voltage loss and parasitic capacitance effect. Mentor Graphics EldoSpice software package is used to simulate the circuitry. The entire design of the row decoder, SA and clock generator are based on 0.18-μm CMOS process. Therefore, the design of the SA and the CP circuits are better suited for low power read and write operation in EEPROM, which will be compatible with the readerless RFID transponder.