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Low Power and Process Variation Aware Sram and Cache Design

Autor Avesta Sasan, Fadi Kurdahi, Ahmed Eltawil
en Limba Engleză Hardback – dec 2015
This book addresses process variability and power management for embedded memories, which are becoming dominant components in today’s Systems on Chip (SoCs).  It provides thorough background on voltage scaling and the reliability effects on memories, while describing memory behavior at different voltages and frequencies. The authors describe a cross-layer approach, simultaneously targeting the manufacturing of devices, the inner-design of the memory circuits, as well as the way they are architected into a system.  This approach enables the design of reliable, power-efficient systems in which memories are dominating area, power, and performance.
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Specificații

ISBN-13: 9781461422716
ISBN-10: 146142271X
Pagini: 200
Ilustrații: 100 schwarz-weiße Abbildungen, Bibliographie
Dimensiuni: 155 x 235 mm
Ediția:2015
Editura: SPRINGER LONDON
Locul publicării:New York, NY, United States

Public țintă

Research

Cuprins

Introduction.- SCPS Cache.- RDC-Cache.- IDC-Cache.- VTD-Cache.- Conclusions.

Textul de pe ultima copertă

This book addresses process variability and power management for embedded memories, which are becoming dominant components in today’s Systems on Chip (SoCs).  It provides thorough background on voltage scaling and the reliability effects on memories, while describing memory behavior at different voltages and frequencies. The authors describe a cross-layer approach, simultaneously targeting the manufacturing of devices, the inner-design of the memory circuits, as well as the way they are architected into a system.  This approach enables the design of reliable, power-efficient systems in which memories are dominating area, power, and performance.

Caracteristici

Describes a variety of design solutions for voltage scalable SRAM/Cache architectures with reliability tolerance to process variationExplains cross layer voltage and power management, enabling system level awareness of manufacturing defects and circuit/architectural mitigation techniquesIncludes techniques for building fault free system using faulty components/memoriesExplores tradeoffs between power consumption, area, reliabality and performance in nano region memory design