High Performance Embedded Architectures and Compilers
Editat de Tom Conte, Nacho Navarro, Wen-Mei W. Hwu, Mateo Valero, Theo Ungereren Limba Engleză Paperback – 4 noi 2005
Preț: 345.49 lei
Preț vechi: 431.86 lei
-20% Nou
Puncte Express: 518
Preț estimativ în valută:
61.14€ • 71.30$ • 53.68£
61.14€ • 71.30$ • 53.68£
Carte tipărită la comandă
Livrare economică 12-17 ianuarie 26
Preluare comenzi: 021 569.72.76
Specificații
ISBN-13: 9783540303176
ISBN-10: 3540303170
Pagini: 332
Ilustrații: XIV, 318 p.
Dimensiuni: 155 x 235 x 19 mm
Greutate: 0.51 kg
Ediția:2005
Editura: Springer
Locul publicării:Berlin, Heidelberg, Germany
ISBN-10: 3540303170
Pagini: 332
Ilustrații: XIV, 318 p.
Dimensiuni: 155 x 235 x 19 mm
Greutate: 0.51 kg
Ediția:2005
Editura: Springer
Locul publicării:Berlin, Heidelberg, Germany
Public țintă
ResearchCuprins
Invited Program.- Keynote 1: Using EEMBC Benchmarks to Understand Processor Behavior in Embedded Applications.- Keynote 2: The Chip-Multiprocessing Paradigm Shift: Opportunities and Challenges.- Software Defined Radio – A High Performance Embedded Challenge.- I Analysis and Evaluation Techniques.- A Practical Method for Quickly Evaluating Program Optimizations.- Efficient Sampling Startup for Sampled Processor Simulation.- Enhancing Network Processor Simulation Speed with Statistical Input Sampling.- II Novel Memory and Interconnect Architectures.- Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems.- Beyond Basic Region Caching: Specializing Cache Structures for High Performance and Energy Conservation.- Streaming Sparse Matrix Compression/Decompression.- XAMM: A High-Performance Automatic Memory Management System with Memory-Constrained Designs.- III Security Architecture.- Memory-Centric Security Architecture.- A Novel Batch Rekeying Processor Architecture for Secure Multicast Key Management.- Arc3D: A 3D Obfuscation Architecture.- IV Novel Compiler and Runtime Techniques.- Dynamic Code Region (DCR) Based Program Phase Tracking and Prediction for Dynamic Optimizations.- Induction Variable Analysis with Delayed Abstractions.- Garbage Collection Hints.- V DomainSpecificArchitectures.- Exploiting a Computation Reuse Cache to Reduce Energy in Network Processors.- Dynamic Evolution of Congestion Trees: Analysis and Impact on Switch Architecture.- A Single (Unified) Shader GPU Microarchitecture for Embedded Systems.- A Low-Power DSP-Enhanced 32-Bit EISC Processor.