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Algorithmic Aspects of VLSI Layout de Der-Tsai Lee

Algorithmic Aspects of VLSI Layout

Autor Der-Tsai Lee, Majid Sarrafzadeh
en Limba Engleză Hardback – noi 1993
Discussing algorithmic aspects of VLSI layout, this text includes coverage of: issues in timing driven layout; LP formulation of global routeing and placement; Stockmeyer's floorplan optimization technique; the Manhattan and knock-knee routeing modes; and parallel algorithms for placement.
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Specificații

ISBN-13: 9789810214883
ISBN-10: 981021488X
Pagini: 408
Dimensiuni: 160 x 218 x 28 mm
Greutate: 0.68 kg
Editura: World Scientific Publishing Company

Cuprins

Issues in timing driven layout, M. Marek-Sadowska; binary formulations for placement and routing problems, M. Sriram, S.M. Kang; a survey of parallel algorithms for placement, P. Banerjee; near optimal fast solution to graph and hypergraph partitioning, F. Makedon, S. Tragoudas; LP formulation of global routing and placement, T. Lengauer, M. Lugering; circuit partitioning algorithms based on geometry model, T. Asano & Tokuyama; on the Manhattan and knock-knee routing modes, D. Zhou, F.P. Preparata; a note on the complexity of Stockmeyer's floorplan optimization technique, T.C. Wang, D.F. Wong; the virtual height of a straight line embedding of a plane graph, T. Takahashi, Y. Kajitani; routing around two rectangles to minimize the layout area, T. Gonzalez, S.L. Lee.